AD484 user manual
V1.2
AD484 User manual
February 2007
www.4dsp.com
- 3 -
Table of Contents
1
Acronyms and related documents ............................................................................. 4
1.1
Acronyms............................................................................................................... 4
1.2
Related Documents ............................................................................................... 4
1.3
General description................................................................................................ 5
2
Installation ................................................................................................................... 6
2.1
Requirements and handling instructions ................................................................ 6
2.2
Firmware and software........................................................................................... 6
3
Design .......................................................................................................................... 6
3.1
FPGA devices ........................................................................................................ 6
3.1.1
Virtex-4 device A ............................................................................................ 6
3.1.2
Virtex-4 device B ............................................................................................ 9
3.2
FPGA devices configuration..................................................................................10
3.2.1
Flash storage ................................................................................................10
3.2.2
CPLD device .................................................................................................10
3.2.3
JTAG.............................................................................................................12
3.3
Clock tree..............................................................................................................13
3.4
Memory resources ................................................................................................13
3.4.1
QDR2 SRAM.................................................................................................13
3.4.2
DDR2 SDRAM ..............................................................................................13
3.5
A/D inputs and outputs main characteristics..........................................................14
3.5.1
Analog inputs ................................................................................................15
3.5.2
Clock input and reference clock distribution ..................................................15
3.5.3
Multi-module Synchronization .......................................................................15
3.6
Front Panel optical transceivers ............................................................................16
4
Power requirements ...................................................................................................17
4.1
External power connector for stand alone mode ...................................................18
5
System Side view........................................................................................................19
6
Environment................................................................................................................19
6.1
Temperature .........................................................................................................19
6.2
Convection cooling................................................................................................19
6.3
Conduction cooling ...............................................................................................19
7
Safety...........................................................................................................................19
8
EMC .............................................................................................................................20
9
Warranty......................................................................................................................20
