User’s Manual
34
ECM-5716 Series User’s Manual
3.7.28 LVDS Connector (JLVDS)
Signal
PIN
Signal
VDDSAFE5
2
1
VDDSAFE3
VDDSAFE5
4
3
VDDSAFE3
DDCPDATA
6
5
DDCPCLK
GND
8
7
GND
YAP0
10
9
YAP1
YAM0
12
11
YAM1
GND
14
13
GND
YAP2
16
15
YAP3
YAM2
18
17
YAM3
GND
20
19
GND
YBP0
22
21
YBP1
YBM0
24
23
YBM1
GND
26
25
GND
YBP2
28
27
YBP3
YBM2
30
29
YBM3
GND
32
31
GND
CLKAP
34
33
CLKBP
CLKAM
36
35
CLKBM
GND
38
37
GND
RESERVED
40
39
RESERVED
3.7.29 Signal Description – LVDS Connector (JLVDS)
DDCPDATA
I/O
CMOS
Panel DDC Data:
This signal is used as the DDC data signal between the LFP
and the GMCH.
DDCPCLK
I/O
CMOS
Panel DDC Clock:
This signal is used as the DDC clock signal between the LFP
and the GMCH.
YAP
O
LVDS
Channel A differential data pair 3:0 output (true):
245-800 MHz.
YAM
O
LVDS
Channel A differential data pair 3:0 output (compliment):
245--800 MHz
YBP
O
LVDS
Channel B differential data pair 3:0 output (true):
245-800 MHz.
YBM
O
LVDS
Channel B differential data pair 3:0 output (compliment):
245- 800 MHz.
CLKAP
O
LVDS
Channel A differential clock pair output (true):
245-800 MHz
CLKAM
O
LVDS
Channel A differential clock pair output (compliment):
245- 800 MHz.
CLKAP
O
LVDS
Channel B differential clock pair output (true):
245-800 MHz
CLKAM
O
LVDS
Channel B differential clock pair output (compliment):
245- 800 MHz.
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