38 CPCI-7806/CPCI-7806RC Pentium/Celeron M Universal CompactPCI Single Board Computer
Publication No. 500-657806-000 Rev. G
3 • Embedded PC/RTOS Features
The CPCI-7806/CPCI-7806RC feature additional capabilities beyond those of a
typical desktop computer system. The unit provides standard general-purpose
timers along with a programmable Watchdog Timer for synchronizing and
controlling multiple events in embedded applications. The CPCI-7806/
CPCI-7806RC also provide a bootable CompactFlash system or PICMG 2.16
Ethernet over the CompactPCI backplane and IPMI 1.5 support to allow
compatibility with the most demanding CompactPCI applications. These features
make the unit ideal for embedded applications, particularly where standard hard
drives and floppy disk drives cannot be used.
NOTE
IPMI is no longer supported. Older boards may have IPMI.
3.1 CompactPCI Bus Bridge
The CPCI-7806/CPCI-7806RC incorporate a PLX PCI-6254 (Hint HB6) Universal
Bridge device that performs universal PCI bridging functions for embedded and
intelligent I/O applications. The PCI device acts as a gateway to an intelligent
subsystem. As a peripheral controller it allows the local CPCI-7806/CPCI-7806RC
processor to configure and control the onboard local subsystem independent
from the CompactPCI bus host processor. The CPCI-7806/CPCI-7806RC local PCI
subsystems are presented to the CompactPCI bus host as a single CompactPCI
device. As a system controller, the bridge acts as a standard transparent PCI-to-
PCI bridge. For detailed information concerning the embedded PCI bus bridge,
consult the PLX PCI-6254 (Hint HB6) datasheet.
The CPCI-7806/CPCI-7806RC PCI bridge devices provide the following features:
3.1.1 PCI Interface
• Full compliance with the PCI Local Bus Specification, Revision 2.2
• Supports 3.3 V or 5 V VIO operation
• Concurrent local (secondary) and CompactPCI (primary) bus operation
3.1.2 Buffer Architecture
• Queuing of multiple transactions in either direction
• 256 byte of posted write (data and address) buffering in each direction
• 256 byte of read data buffering in each direction
• Four delayed transaction entries in each direction
3.1.3 Configuration Register and Control/Status Registers
(CSRs)
• Two sets of standard PCI configuration registers corresponding to the local
and CompactPCI interfaces: accessible from either the local or CompactPCI
interface
• Three 32-bit base address configuration registers mapping the CSRs