42 VMICPCI-7055/CPCI-7055RC Hardware Reference Manual
Publication No. 500-657055-000 Rev. G
A.3 J3 Connector Pinout
The J3 connector is a five row, 19 pins each, 2 mm “Hard Metric” CompactPCI
connector. An additional external metal shield is also used, labeled row F. Figure
below illustrates the J3 connector and the connector pinout. This connector is used
to route the two serial ports and the two Gigabit Ethernet ports to the backplane
rear I/O.
1
CPCI_CLK
1
GND
CPCI_REQ1# CPCI_GNT1# CPCI_REQ2#
GND
* VCC_VIO - The VMICPCI-7055/CPCI-7055RC are universal VIO designs.
The VMICPCI-7055/CPCI-7055RC support a 64-bit CompactPCI bus.
Table A-2 J2 Connector and Pinout
Pin
No.
Row A
Row B
Row C
Row D
Row E
Row
F
Table A-3 J3 Connector and Pinout
Pin
No.
Row A
Row B
Row C
Row D
Row E
Row
F
19
GND
GND
GND
GND
GND
GND
18
LP
LPA_BI_DA
2-
GND
LP
LPA_BI_DC-
GND
17
LP
LPA_BI_DB
2-
GND
LP
LPA_BI_DD- GND
16
LP LPB_BI_DA
2-
GND
LP
LPB_BI_DC- GND
15
LP LPB_BI_DB
2-
GND
LP
LPB_BI_DD- GND
14
GND
GND
GND
GND
GND
GND
13
SP2_RTS
SP1_RI
SP2_DSR
SP2_DCD
SP2_CTS
GND
12
SP1_RTS
SP2_DTR
VCC_5.0
SP1_CTS
GND
GND
11
SP2_TXB
SP2_RXD
SP1_DTR
SP1_DCD
LPA_BI_DC-
GND
10
SP1_TXB
SP1_RXD
SP1_DSR
SP2_RI
LPA_BI_DD2
-
GND
9
GND
GND
N/C
GND
LPB_BI_DC2
-
GND
8
LPA_BI_DA2
+
LPA_BI_DA
2-
SP2_ACTIV
E
LPA
LPB_BI_DD2
-]
GND
7
LPA_BI_DB2
+
LPA_BI_DB
2-
SP2_LOOPB
ACK
LPA
GND
GND
6
LPB_BI_DA2
+
LPB_BI_DA
2-
SP2_R485/
232
LPB
GND
GND
5
LPB_BI_DB2
+
LPB_BI_DB
2-
SP1_ACTIV
E
LPB
N/C
GND
4
GND
GND
VCC_5.0
GND
VCC_3.3
GND
3
G1_Y_LINK1
00#
G1_G_LK10
00#
SP1_R485/
232
GND
VCC_3.3
GND
2
G1_G_LINK1
0#
G1_Y_ACT
SP1_LOOPB
ACK
G2_Y_LINK100
#
G2_G_LK10
00#
GND