Power Automation and Protection Division
I.L. 40-201.9
REL 352 Version 1.00
L-3
L
A
P
P
E
N
D
I
X
Figure L-2: REL 352 Logic Diagram
3
“1”
2 CDT
COMM
IK0
TEST
IKEY
To Channel
Transmitter
From Phase
Currents
IA
IB
IC
C0, C1, C2
IT
Sequence
Network Filter
IKEY, LP
LN
IKEY
LP
LDT1
LDT2
LDT1
LDT2
S1
S2
M1
M2
CHOK
CHOK
3
2
“1”
TERM
3
2
“1”
TERM
3
2
“0”
COMM
CIN
SYSTEM SETTINGS IN BOLD LETTERS
SPACE 1
MARK 1
SPACE 2
MARK 2
S1
M1
S2
M2
From Channel
Receiver
ECF
EXTERNAL
CHANNEL FAILURE 1
EXTERNAL
CHANNEL FAILURE 2
NOTE:
Hardware Function
SETTING
S1
3
2
M1
COMM
“0”
X0R
75/0
S2
3
2
M2
COMM
“0”
X0R
75/0
3
2 TERM
“1”
ECF
2
3
“1”
CHOK
“0” – Logic 0
“1” – Logic 1
XOR DEFINITION
INPUT 1
INPUT 2
OUTPUT
0
0
1
1
0
1
0
1
0
1
1
0
CHANNEL FAILURE / LOW RECEIVE
LEVEL DETECTION
TERM
# OF TERMINALS 2 OR 3 TERMINAL LINE
COMM
Fault
Detector 2
FD2
COMM
COMM INTFCE 2 STATE (AM PLC) OR 3 STATE (FM PLC)
COMMUNICATION INTERFACE
AND COMPARISON
FD2
LN = – LP
COMPARERS
LN1
LN2
LP1
LP2
TD296.OH sub 2
Sheet 1 of 3
(2)
(2)
(2) timers are 20% higher for 50Hz systems