Reference clock deviation higher than the set maximum time deviation
Route switching that causes the virtual difference between the internal clocks of respective
line differential protection IEDs to be higher that the set maximum time deviation (±200-2000
μs) due to asymmetry in the communication channel delay, jitter and wander, and buffer
memory, causes the blocking of the internal clock synchronization. If this deviation lasts under
2 s, the protection function still remains in operation. The total stability time of 2 seconds
stems from the route switching being supervised during 50 internal clock synchronization
messages that are sent every 5 ms but evaluated every 40 ms.
If deviation between the internal clocks is higher than the set limit after 2 s, a communication
failure alarm is issued and the protection function gets blocked. After communication
channels are restored, a re-synchronization with initial 20 μs clock adjustment steps takes
place for each clock synchronization message. The clock adjustment steps gradually decrease
as the internal clock differences are reduced.
2.3.2
Longer route switching interruptions
GUID-3AB55816-1D98-4D07-8526-7201E2EF2E1E v1
When echo timing is used and route switching takes longer than 2 s, internal clocks are
synchronized with asymmetric delay included. Influence from asymmetric delay is 2 s/40 ms x
10 μs (average 20 ms and 1 μs) = 0.5 ms, which can cause an unwanted trip depending on the
sensitivity set for the protection function.
When global time (GPS) is used, communication failure in the range of 10–30 seconds can
cause a synchronization loss of the internal clocks. Communication failure longer than 30
seconds always requires a re-synchronization of the internal clocks. If synchronization is lost,
5–15 seconds of healthy communication is required to get the internal clocks synchronized
again and to get them working with normal tripping times.
2.3.3
Detecting accumulated time delay changes with echo timing
GUID-F9ED604A-1E97-4354-BD30-93C010D3313C v1
Echo timing has an additional feature that detects accumulated time delay changes below the
MaxtDiffLevel of ±200-2000 μs. This is done to avoid small changes from creating an
accumulated asymmetry which can cause an unwanted trip. Due to asymmetry in
communication channel delay, jitter and wander, and buffer memory, this feature is restricted
to four time delay changes.
The parameter used for detecting the accumulated time delay changes (sensitivity) is
DeadbandtDiff, and its setting must be coordinated with that of MaxtDiffLevel. The influence
of
MaxtDiffLevel on sensitivity is shown in Figure
0%
1500
3000
4500
6000
0
5
10
15
20
kA
1 ms
0.8 ms
0.6 ms
0.4 ms
0.2 ms
A
0%
1500
3000
4500
6000
0
5
10
15
20
kA
1 ms
0.8 ms
0.6 ms
0.4 ms
0.2 ms
A
IEC07000225-1-en.vsdx
Fault current at external faults
IEC07000225 V1 EN-US
Figure 5:
Virtual error in amperes at different asymmetric delay times in a
telecommunication network
1MRK 505 382-UEN E
Section 2
Telecommunication networks and line differential protection
Communication set-up, 670/650 series
15
Application Guide
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Summary of Contents for Relion 670 series
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