6. Compare the operate value to the set frequency high limit value.
7.
Decrease the frequency of the applied voltage until it crosses the frequency low limit and
the
START
signal disappears.
8. Check that the
FREQOK
signal disappears.
9. Compare the reset value to the set frequency low limit value.
10. Readjust the frequency of the applied voltage (with steps of 0.001 Hz/s) to a value within
the set frequency band limit.
11. Ensure that the
START
signal reappears.
12. Wait for a time corresponding to
tCont and ensure that the
TRIP
and
TRIPCONT
signals
are generated.
13. Measure the time delay for the
TRIP
signal and compare it to the set value.
Verification of the
ACCALARM
value and time delay to operation
1.
Connect the test set for the injection of three-phase currents and three-phase voltages to
the appropriate current and voltage terminals of the IED.
2.
Ensure that the settings in the IED are appropriate for the default settings, especially the
CurrStartLevel, FreqHighLimit, FreqLowLimit, UHighLimit and ULowLimit setting.
3.
Supply the IED with three-phase currents and voltages at their rated value.
4. Slowly decrease the frequency of the applied voltage until it crosses the frequency high
limit and the
START
signal appears.
5. Continuously change the frequency of the applied voltage, so that for a certain time the
frequency is outside the set band limit and falls gradually within the band limit.
6. Count only the time when the frequency lies within the set frequency band limit. Wait for a
time corresponding to
tAccLimit and ensure that the
ACCALARM
signal appears.
7.
Measure the time delay for the
ACCALARM
signal and compare it to the set value.
Extended testing
1.
To check the value of
TRIPACC
, repeat the above test case in such a way that the
frequency of the applied voltage is within the set frequency band when time approaches
the
tAccLimit setting value.
Verification of generator start and stop logic
1.
Ensure that the settings in the IED are appropriate to the default settings, especially the
CurrStartLevel, FreqHighLimit, FreqLowLimit, UHighLimit and ULowLimit.
2.
Ensure that the setting
CBCheck is enabled.
3.
Supply the IED with three-phase currents and voltages at their rated values.
4. Slowly decrease the frequency of the applied voltage until the
START
signal appears.
5. Activate the
CBOPEN
input signal.
6. Slowly decrease the injected current below the
CurrStartLevel value until the
START
signal
disappears.
7.
Compare the current magnitude value to the set value.
Verification of voltage band limit check logic
1.
Ensure that the settings in the IED are appropriate to the default settings, especially the
CurrStartLevel, FreqHighLimit, FreqLowLimit, UHighLimit and ULowLimit settings.
2.
Ensure that the
EnaVoltCheck is enabled.
3.
Supply the IED with three-phase currents and voltages at their rated values.
4. Check that the
VOLTOK
signal appears.
5. Slowly decrease the frequency of the applied voltage until the
START
signal appears.
6. Slowly decrease the positive-sequence voltage of the injected voltage below the
ULowLimit value until the
START
signal disappears.
7.
Check that the
VOLTOK
signal disappears.
8. Compare the reset value to the set voltage low limit value.
9. Readjust the positive-sequence voltage of the applied voltage to a value within the set
voltage band limits.
Section 12
1MRK 502 067-UEN B
Testing functionality by secondary injection
196
Commissioning manual
