3-10
Chapter 3
Current FSB Frequency:
This item will show you the current system front side bus speed.
Current DRAM Frequency:
This item will show you the current DRAM bus speed.
DRAM Clock:
This item sets the DRAM clock of your DRAM module. The system may be unstable or unable to boot up
if your DRAM module does not support the clock you set.
When set to [By SPD], the BIOS will read the DRAM module SPD data and automatically set the DRAM
clock by the value stored in it.
DRAM Timing Selectable:
Four options are available: Manual
By SPD
Turbo
Ultra. The default setting is
By SPD
. When
set to “
By SPD
”, the BIOS will read the DRAM module SPD data and automatically set to the values
stored in it. If you set to “
Manual
”, the following five items will be available to let you make
adjustments.
CAS Latency Time:
Four options are available: 1.5
2
2.5
3. The default setting is
2.5
. You can select SDRAM CAS
(
C
olumn
A
ddress
S
trobe) latency time according your SDRAM specification.
Bank Interleave:
Three options are available: Disabled
2 Way
4 Way. The default setting is
Disabled
. Depending on
your SDRAM module structure, the 4-Way setting can offer the best performance. If you choose the
wrong setting, the computer system will not run in a stable manner. For detailed information on your
SDRAM module, please ask your SDRAM module manufacturer.
Precharge to Active (Trp):
Trip timing value (Precharge time – time from precharge command to when back can be activated).
Active to Precharge (Tras):
Tras timing value = Minimum bank active time from activate to precharge of same bank.
Active to CMD (Trcd):
Trcd timing value = RAS to CAS latency
+
rd/wr command delay
DRAM Burst Length
DDR SDRAM modules provide a Burst mode that means an auto precharge function for programmable
READ or WRITE burst lengths of 4 or 8 locations.
This means that if we set burst length to 8, the address bus will acesss 8 bytes each cycle to precharge,
etc.
DRAM Command Rate:
Two options are available: 2T Command or 1T Command. The default setting is
2T Command
. When the
host (northbridge) locates the desired memory address, it then processes the wait state of commands. Set
KV7 Series
