3-10 Chapter
3
LDT Bus Frequency:
Select the LDT bus frequency among [200 MHz], [400 MHz], [600 MHz] [800 MHz],
[1 GHz], or [Auto].
PCI1 Master 0 WS Write / PCI2 Master 0 WS Write:
[Enabled]:
Writes to the PCI bus are executed with zero wait state (immediately)
when PCI bus is ready to receive data.
[Disabled]:
The system will wait one state before data is written to the PCI bus.
PCI1 Post Write / PCI2 Post Write:
[Enabled]:
Data transmissions from CPU to PCI bus are buffered and compensate for
the different speed between CPU and PCI bus.
[Disabled]: D
ata transmissions are not buffered and CPU must wait until the data
transmission is complete and then start another transmission cycle.
Back to Advanced Chipset Features Setup Menu:
VLink Data Rate:
Selects the speed of VLink that links the North Bridge and South Bridge.
Watch Dog Function
This option controls the function for Watch Dog.
[Disabled]:
Disable the Watch Dog function.
[Enabled/Sec.]:
Enable the Watch Dog function by the timer based on seconds.
[Enabled/Min.]:
Enable the Watch Dog function by the timer based on minutes.
Watch Dog Time-Out Value
Type in the Time-Out value for your Watch Dog function.
SV-1A
