A96G140/A96G148/A96A148 User’s manual
15. USI
189
USInST1 (USIn Status Register 1: For UART and SPI mode): E1H/F1H, n = 0, 1
7
6
5
4
3
2
1
0
DREn
TXCn
RXCn
WAKEn
USInRST
DORn
FEn
PEn
R/W
R/W
R
R/W
R/W
R
R/W
R/W
Initial value: 80H
DREn
The DREn flag indicates if the transmit buffer (USInDR) is ready to
receive new data. If DREn is
‘1’, the buffer is empty and ready to be
written. This flag can generate a DREn interrupt.
0
Transmit buffer is not empty.
1
Transmit buffer is empty.
TXCn
This flag is set when the entire frame in the transmit shift register has
been shifted out and there is no new data currently present in the
transmit buffer. This flag is automatically cleared when the interrupt
service routine of a TXCn interrupt is executed. This flag can generate
a TXCn interrupt. This bit is automatically cleared.
0
Transmission is ongoing.
1
Transmit buffer is empty and the data in transmit shift register
are shifted out completely.
RXCn
This flag is set when there are unread data in the receive buffer and
cleared when all the data in the receive buffer are read. The RXCn flag
can be used to generate an RXCn interrupt.
0
There is no data unread in the receive buffer
1
There are more than 1 data in the receive buffer
WAKEn
This flag is set when the RXDn pin is detected low while the CPU is in
STOP mode. This flag can be used to generate a WAKEn interrupt.
This bit is set only when in asynchronous mode of operation. This bit
should be cleared by program software. (only UART mode)
0
No WAKE interrupt is generated.
1
WAKE interrupt is generated
USInRST
This is an internal reset and only has effect on USIn. Writing
‘1’ to this
bit initializes the internal logic of USIn and this bit is automatically
cleared to
‘0’.
0
No operation
1
Reset USIn
DORn
This bit is set if a Data Overrun occurs. While this bit is set, the
incoming data frame is ignored. This flag is valid until the receive buffer
is read.
0
No Data Overrun
1
Data Overrun detected
FEn
This bit is set if the first stop bit of next character in the receive buffer
is detected as
‘0’. This bit is valid until the receive buffer is read. (only
UART mode)
0
No Frame Error
1
Frame Error detected
PEn
This bit is set if the next character in the receive buffer has a Parity
Error to be received while Parity Checking is enabled. This bit is valid
until the receive buffer is read. (only UART mode)
0
No Parity Error
1
Parity Error detected
