MC80F0304/08/16
56
November 4, 2011 Ver 2.12
time, selecting of output, and clearing of the binary counter.
Clearing the binary counter is repeated within the detection time.
If the malfunction occurs for any cause, the watchdog timer out-
put will become active at the rising overflow from the binary
counters unless the binary counter is cleared. At this time, when
WDTON=1, a reset is generated, which drives the RESET pin to
low to reset the internal hardware. When WDTON=0, a watchdog
timer interrupt (WDTIF) is generated. The WDTON bit is in reg-
ister CLKCTLR.
The watchdog timer temporarily stops counting in the STOP
mode, and when the STOP mode is released, it automatically re-
starts (continues counting).
Figure 12-2 WDTR: Watchdog Timer Control Register
Example: Sets the watchdog timer detection time to 1 sec. at
4.194304MHz
Enable and Disable Watchdog
Watchdog timer is enabled by setting WDTON (bit 4 in
CKCTLR) to “1”. WDTON is initialized to “0” during reset and
it should be set to “1” to operate after reset is released.
Example: Enables watchdog timer for Reset
:
LDM
CKCTLR,#xxx1_xxxxB;
WDTON
←
1
:
:
The watchdog timer is disabled by clearing bit 4 (WDTON) of
CKCTLR. The watchdog timer is halted in STOP mode and re-
starts automatically after STOP mode is released.
Watchdog Timer Interrupt
The watchdog timer can be also used as a simple 7-bit timer by
clearing bit4 of CKCTLR to “0”. The interval of watchdog timer
interrupt is decided by Basic Interval Timer. Interval equation is
shown as below.
T
WDT
= (WDTR+1)
×
Interval of BIT
The stack pointer (SP) should be initialized before using the
watchdog timer output as an interrupt source.
Example: 7-bit timer interrupt set up.
LDM
CKCTLR,#xxx0_xxxxB;
WDTON
←
0
LDM
WDTR,#8FH
;
WDTCL
←
1
:
7
6
5
4
3
2
1
0
WDTCL
Clear count flag
0: Free-run count
INITIAL VALUE: 0111 1111
B
ADDRESS: 0F4
H
WDTR
W
W
W
W
1: When the WDTCL is set to “1”, binary counter
is cleared to “0”. And the WDTCL becomes “0” automatically
after one machine cycle. Counter count up again.
7-bit compare data
W
W
W
W
LDM
CKCTLR,#3FH ;
Select 1/1024 clock source
,
WDTON
←
1, Clear Counter
LDM
WDTR,#08FH
LDM
WDTR,#08FH ;
Clear counter
:
:
:
:
LDM
WDTR,#08FH ;
Clear counter
:
:
:
:
LDM
WDTR,#08FH ;
Clear counter
Within WDT
detection time
Within WDT
detection time
