Abov MC95FG0128A, User Manual

Page 1: ...MC95FG0128A Aug 02 2018 Ver 2 9 1 ABOV SEMICONDUCTOR Co Ltd 8 BIT MICROCONTROLLERS MC95FG0128A User s Manual Ver 2 9...

Page 2: ...e type Apr 26 2011 2 0 Correct A D Converter Characteristics Mar 03 2011 1 9 Correct Interrupt register Port selection register name Feb 10 2011 1 8 AC description modification Jan 18 2011 1 7 Timer r...

Page 3: ...or offices in Korea or Distributors ABOV Semiconductor reserves the right to make changes to any information here in at any time without notice The information diagrams and other data in this manual a...

Page 4: ...ns 37 7 3 A D Converter Characteristics 38 7 4 Voltage Dropout Converter Characteristics 38 7 5 Power On Reset Characteristics 39 7 6 Brown Out Detector Characteristics 39 7 7 Internal RC Oscillator C...

Page 5: ...A D Converter 150 11 11 CALCULATOR_AI 155 12 Power Down Operation 159 12 1 Overview 159 12 2 Peripheral Operation in IDLE STOP Mode 159 12 3 IDLE mode 160 12 4 STOP mode 160 12 5 Release Operation of...

Page 6: ...MC95FG0128A 6 Aug 02 2018 Ver 2 9 16 Configure option 196 16 1 Configure option Control Register 196 17 APPENDIX 197...

Page 7: ...Figure 8 1 Program memory 46 Figure 8 2 Data memory map 47 Figure 8 3 Lower 128 bytes RAM 48 Figure 8 4 XDATA memory area 49 Figure 10 1 External Interrupt Description 60 Figure 10 2 Block Diagram of...

Page 8: ...lock Formats when UCPHA 0 120 Figure 11 30 SPI Clock Formats when UCPHA 1 121 Figure 11 31 SPI Block Diagram 128 Figure 11 32 SPI Transmit Receive Timing Diagram at CPHA 0 130 Figure 11 33 SPI Transmi...

Page 9: ...en BOD RESET 170 Figure 14 1 Block Diagram of On chip Debug System 173 Figure 14 2 10 bit transmission packet 174 Figure 14 3 Data transfer on the twin bus 174 Figure 14 4 Bit transfer on the serial b...

Page 10: ...he MC95FG0128A also supports power saving modes to reduce power consumption Device Name FLASH EEPROM XRAM SRAM ADC Package MC95FG0128A 128K bytes 4K bytes 8K bytes 256 bytes 15 channel 100LQFP 80LQFP...

Page 11: ...tor 8MHz OSC 1 5 25 On Chip WDT Oscillator 8MHz OSC 50 40 85 On Chip PLL 1 38MHz 20 18MHz with 32 768KHz Power On Reset 1 4V Programmable Brown Out Detector 1 6V 2 5V 3 6V 4 2V Minimum Instruction Exe...

Page 12: ...ng Information of MC95FG0128A Device name ROM size SRAM size XRAM size EEPROM size Package MC95FG0128AL 128 Kbytes FLASH 256 bytes 8 Kbytes 4 Kbytes 100 LQFP MC95FG8128AL MC95FG8128AQ 80 LQFP 80 MQFP...

Page 13: ...f MCU internal memory and I O peripherals And the OCD also controls MCU internal debugging logic it means OCD controls emulation step run monitoring etc The OCD Debugger program works on Microsoft Win...

Page 14: ...ming mode very high speed signal will be provided to pin DSCL and DSDA And it will cause some damages to the application circuits connected to DSCL or DSDA port if the application circuit is designed...

Page 15: ...95FG0128A Aug 02 2018 Ver 2 9 15 1 4 3 Programmer E PGM Support ABOV ADAM devices 2 5 times faster than S PGM Main controller 32 bit MCU 72MHz Buffer memory 1MB Figure 1 4 E PGM component and connecto...

Page 16: ...ounted on target board using 10pin cable Features PGMplusLC2 is low cost writing Tool USB interface is supported Not need USB driver installation Connect the external power adapter 5V 2A Supported hig...

Page 17: ...x35mm Weight 2 0kg Input Voltage DC Adaptor 15V 2A Operating Temp 10 40 Storage Temp 30 80 Water Proof No Product name E PGM GANG 6 Dimension x y h 148 2 x 22 5 x35mm Weight 2 8kg Input Voltage DC Ada...

Page 18: ...A P06 SCL P07 P00 SUBXIN P04 SUBXOUT P05 XIN P62 XOUT P63 nRESET VDD VSS USART0 P03 RxD0 P02 TxD0 P01 ACK0 P00 USS0 P50 BUZ BUZZER P32 AN10 P33 AN11 P34 AN12 P36 AN14 XRAM 8KB VDD18 P1 PORT P17 P10 P2...

Page 19: ...0 P37 MISO0 P36 MOSI0 P35 SCK0 P34 SSS0 I2C P07 SDA P06 SCL P07 P00 SUBXIN P04 SUBXOUT P05 XIN P62 XOUT P63 nRESET VDD VSS USART0 P03 RxD0 P02 TxD0 P01 ACK0 P00 USS0 P50 BUZ BUZZER P32 AN10 P33 AN11 P...

Page 20: ...P57 T5 PWM5 SPI0 P37 MISO0 P36 MOSI0 P35 SCK0 P34 SSS0 I2C P07 SDA P06 SCL P07 P00 SUBXIN P04 SUBXOUT P05 XIN P62 XOUT P63 nRESET VDD VSS USART0 P03 RxD0 P02 TxD0 P01 ACK0 P00 USS0 P50 BUZ BUZZER P32...

Page 21: ...97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 nTEST VDD18 DSCL DSDA LPF VDD P63 XOUT VSS P93 RxD3 P62 XIN P91 ACK3 P92 TxD3 P87 P90 USS3 P66 P67 P65 EC5 nRESET P64 EC4 P60 EC2 P61...

Page 22: ...79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 nTEST VDD18 DSCL DSDA LPF VDD P63 XOUT VSS P62 XIN P66 P67 P65 EC5 nRESET P64 EC4 P60 EC2 P61 EC3 P56 T4 PWM4 P57 T5 PWM5 P54 T2 PWM2 P55 T3 PW...

Page 23: ...18 P11 INT1 P16 INT6 P17 INT7 P23 AN3 P74 PCI74 P75 PCI75 P76 PCI76 P77 PCI77 P26 AN6 P27 AN7 60 59 57 58 56 54 53 52 51 50 48 46 45 44 43 41 42 47 49 55 63 61 62 64 P53 T1 PWM1 P52 T0 P51 EC0 P50 BUZ...

Page 24: ...VSS 26 27 P27 AN7 P26 AN6 28 29 P31 ACK1 AN9 P30 USS1 AN8 30 31 P33 RxD1 AN11 P32 TxD1 AN10 32 48 47 46 45 44 43 41 42 37 40 39 38 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 nTEST VDD18 DSCL DSD...

Page 25: ...VSS 26 27 P27 AN7 P26 AN6 28 29 P31 ACK1 AN9 P30 USS1 AN8 30 31 P33 RxD1 AN11 P32 TxD1 AN10 32 48 47 46 45 44 43 41 42 37 40 39 38 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 nTEST VDD18 DSCL DSD...

Page 26: ...MC95FG0128A 26 Aug 02 2018 Ver 2 9 4 Package Diagram Figure 4 1 100 pin LQFP package...

Page 27: ...MC95FG0128A Aug 02 2018 Ver 2 9 27 Figure 4 2 80 pin LQFP package...

Page 28: ...MC95FG0128A 28 Aug 02 2018 Ver 2 9 Figure 4 3 80 pin MQFP package...

Page 29: ...MC95FG0128A Aug 02 2018 Ver 2 9 29 Figure 4 4 64 pin LQFP package...

Page 30: ...MC95FG0128A 30 Aug 02 2018 Ver 2 9 Figure 4 5 64 pin LQFP14 package...

Page 31: ...e register can be used via software when this port is used as output port Input INT0 P11 INT1 P12 INT2 P13 INT3 P14 INT4 P15 INT5 P16 INT6 P17 INT7 P20 I O Port P2 8 Bit I O Port Can be set in input o...

Page 32: ...software when this port is used as output port Input BUZ P51 EC0 P52 T0 P53 T1 PWM1 P54 T2 PWM2 P55 T3 PWM3 P56 T4 PWM4 P57 T5 PWM5 P60 I O Port P6 6 Bit I O Port Can be set in input or output mode i...

Page 33: ...enable register can be used via software when this port is used as output Not used in 64 80 pin pakage Input USS3 P91 ACK3 P92 TxD3 P93 RxD3 P94 P95 P96 P97 PA0 I O Port PA 8 Bit I O Port Can be set i...

Page 34: ...resistor Input DSCL I OCD clock input If it doesn t use it need pull up resistor Input nTEST I TEST mode enable nTEST is the same function like internal POR except remaining port configuration setting...

Page 35: ...hift 1 8V to ExtVDD LevelShift ExtVDD to 1 8V DATA REGISTER OPEN DRAIN REGISTER PULL UP REGISTER SUB FUNC DATA OUTPUT DIRECTION REGISTER SUB FUNC DIRECTION 0 1 MUX MUX 0 1 0 1 MUX r D CP Q DEBOUNCE CL...

Page 36: ...to 1 8V DATA REGISTER OPEN DRAIN REGISTER PULL UP REGISTER SUB FUNC DATA OUTPUT DIRECTION REGISTER SUB FUNC DIRECTION 0 1 MUX MUX 0 1 0 1 MUX r D CP Q DEBOUNCE CLK DEBOUNCE ENABLE PORTx INPUT SUB FUN...

Page 37: ...damage to the device This is a stress rating only and functional operation of the device at any other conditions beyond those indicated in the operational sections of this specification is not implied...

Page 38: ...Analog Reference Voltage AVREF note 1 8 5 5 V Analog Ground Voltage AVSS VSS V Analog Input Leakage Current AVDD VDD 5 12V 10 uA ADC Operating Current IDD AVDD VDD 5 12V 1 3 mA SIDD 1 uA note When AVR...

Page 39: ...tics Parameter Symbol Condition MIN TYP MAX Unit Operating Voltage VSS 5 5 V Operating Temperature 40 85 Detection Level 4 2V 4 0 4 4 V 3 6V 3 4 3 8 V 2 5V 2 3 2 7 V 1 6V 1 4 1 8 V Hysteresis mV Opera...

Page 40: ...ng Voltage 1 8 5 5 V Operating Temperature 40 85 Frequency 0 5 1 1 5 MHz Stabilization Time ms Operating Current IDD uA SIDD 1 uA 7 9 PLL Characteristics Table 7 9 PLL Characteristics Parameter Symbol...

Page 41: ...ALL I O IOH 8 57mA VDD 4 5V 3 5 V Input High Leakage Current IIH ALL PAD 1 uA Input Low Leakage Current IIL ALL PAD 1 uA Pull Up Resister RPU ALL PAD except DSCL DSDA 20 50 k Power Supply Current IDD1...

Page 42: ...Clock Transition Time tRCP tFCP XIN 10 ns External Interrupt Input Width tIW INT0 INTx 2 tSYS External Interrupt Transition Time tFI tRI INT0 INTx 1 us nRESET Input Pulse L Width tRST nRESET 8 tSYS E...

Page 43: ...r L Pulse Width tSCKL tSCKH SCK tSYS 30 ns Output Clock Pulse Transition Time tFSCK tRSCK SCK 30 ns First Output Clock Delays Time tFOD OUTPUT Output Clock Delay Time tDS OUTPUT 100 ns Input Pulse Tra...

Page 44: ...specified operating range e g outside specified VDD range This is for information only and devices are guaranteed to operate properly only within the specified range The data presented in this sectio...

Page 45: ...ounter is capable of addressing up to 64K bytes for one bank of memory space but this device has 128K bytes program memory space with bank selection scheme Figure 8 1 shows a map of the lower part of...

Page 46: ...r 2 9 Figure 8 1 Program memory User Function Mode 128KBytes Included Interrupt Vector Region Non volatile and reprogramming memory Flash memory based on EEPROM cell FFFFH 0000H 64K Bytes 64K Bytes Ba...

Page 47: ...e 8 3 The lowest 32 bytes are grouped into 4 banks of 8 registers Program instructions call out these registers as R0 through R7 Two bits in the Program Status Word select which register bank is in us...

Page 48: ...40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F R5 R4 R3...

Page 49: ...a memory and 8K bytes of XSRAM This area has no relation with RAM FLASH It can read and write through SFR with 8 bit unit For more information about EEPROM Data memory see chapter 15 Figure 8 4 XDATA...

Page 50: ...PU P5PU P6PU P7PU 34 F8H IP1 UCTRL11 UCTRL12 UCTRL13 USTAT1 UBAUD1 UDATA1 F0H B SPISR1 FEARL FEARM FEARH FEDR FETR XCON E8H P9 PAIO FEMR FECR FESR FETCR XADD XDATA E0H ACC PA UCTRL01 UCTRL02 UCTRL03 U...

Page 51: ...nter 81H 7 6 5 4 3 2 1 0 SP R W R W R W R W R W R W R W R W Initial value 07H SP Stack Pointer DPL Data Pointer Low Byte 82H 7 6 5 4 3 2 1 0 DPL R W R W R W R W R W R W R W R W Initial value 00H DPL D...

Page 52: ...nk Select bit 1 RS0 Register Bank Select bit 0 OV Overflow Flag F1 User Definable Flag P Parity Flag Set cleared by hardware each instruction cycle to indicate an odd even number of 1 bits in the accu...

Page 53: ...ry constants MEX3 Memory Extension Register 3 96H 7 6 5 4 3 2 1 0 MCB19 UB1 UB0 MXB19 MXM MXB18 MXB17 MXB16 R W R W R W R W R W R W R W R W Initial value 00H MCB19 Memory Constant Bank MSB See MEX2 UB...

Page 54: ...its cleared in this read write register will select the corresponding pin in Px to become an input setting a bit sets the pin to output All bits are cleared by a system reset 9 2 3 Pull up Resistor Se...

Page 55: ...gister P1IO 91H R W 00H P1 Direction Register P1PU 2F01H R W 00H P1 Pull up Resistor Selection Register P1OD 2F0DH R W 00H P1 Open drain Selection Register P1DB 2F19H R W 00H P1 Debounce Enable Regist...

Page 56: ...Pin Change Interrupt Enable Register P8 D8H R W 00H P8 Data Register P8IO D1H R W 00H P8 Direction Register P8PU 2F08H R W 00H P8 Pull up Resistor Selection Register P8OD 2F14H R W 00H P8 Open drain S...

Page 57: ...Px 7 0 I O Data PxIO Px Direction Register 89H 91H 99H A1H B1H B9H C1H C9H D1H D9H E9H 7 6 5 4 3 2 1 0 Px7IO Px6IO Px5IO Px4IO Px3IO Px2IO Px1IO Px0IO R W R W R W R W R W R W R W R W Initial value 00H...

Page 58: ...errupt Enable Register AFH 7 6 5 4 3 2 1 0 PCI77 PCI76 PCI75 PCI74 PCI73 PCI72 PCI71 PCI70 R W R W R W R W R W R W R W R W Initial value 00H PCI7 7 0 Configure Pin Change Interrupt of P7port 0 Disable...

Page 59: ...ough the other bits of the interrupt enable registers The MC95FG0128A supports a four level priority scheme Each maskable interrupt is individually assigned to one of four priority levels by writing t...

Page 60: ...errupt Polarity register as shown in Figure 10 1 Also each external interrupt source has control setting bits The EIFLAG External interrupt flag register register provides the status of external inter...

Page 61: ...7 8 9 10 11 30 31 0 1 2 3 4 5 6 7 8 9 10 11 30 31 IE1 A9H IE5 ADH IP B8H IP1 F8H EIFLAG 0 A4H Release Stop Sleep FLAG0 FLAG1 FLAG2 FLAG3 INT5 IIF RXC1 TXC1 RXC TXC TCIR EA IE 7 A8H PCI P0 I2C USART1...

Page 62: ...T INT20 IE3 2 21 Maskable 00A3H WDT INT21 IE3 3 22 Maskable 00ABH BIT INT22 IE3 4 23 Maskable 00B3H SPI1 INT23 IE3 5 24 Maskable 00BBH USART2 Rx INT24 IE4 0 25 Maskable 00C3H USART2 Tx INT25 IE4 1 26...

Page 63: ...er to continue process again after executing ISR IE EA Flag 1 IEx y 1 1 Program Counter low Byte SP SP 1 M SP PCL 2 Program Counter high Byte SP SP 1 M SP PCH 3 Interrupt Vector Address occurrence Int...

Page 64: ...trolling Interrupt bit Figure 10 4 Interrupt Enable Register effective Timing INTnE reg EA bit set Next Instruction Next Instruction Setting both EA bit and individual interrupt enable bit INTnE makes...

Page 65: ...es is possible Figure 10 5 Execution of Multi Interrupt Following example is shown to service INT0 routine during INT1 routine in Figure 10 6 In this example INT0 interrupt priority is higher than INT...

Page 66: ...aving Restore Process Diagram Sample Source Interrupt Latched Interrupt goes Active System Clock Max 4 Machine Cycle 4 Machine Cycle Interrupt Processing LCALL LJMP Interrupt Routine 02H 01H 00B3H 00B...

Page 67: ...0 12 1 Interrupt Enable Register IE IE1 IE2 IE3 IE4 IE5 Interrupt enable register consists of Global interrupt control bit EA and peripheral interrupt control bits Totally 32 peripheral are able to co...

Page 68: ...s level type EIPOLA is able to have Low High level value If EIEGDE is edge type EIPOLA is able to have rising falling edge value 10 12 6 External Interrupt Enable Register EIENAB When the external int...

Page 69: ...scription for Interrupt IE Interrupt Enable Register A8H 7 6 5 4 3 2 1 0 EA INT5E INT4E INT3E INT2E INT1E INT0E R W R W R W R W R W R W R W Initial value 00H EA Enable or disable all interrupt bits 0...

Page 70: ...E INT13E INT12E R W R W R W R W R W R W Initial value 00H INT17E Enable or disable Timer 5 Interrupt 0 Disable 1 Enable INT16E Enable or disable Timer 4 Interrupt 0 Disable 1 Enable INT15E Enable or d...

Page 71: ...INT26E INT25E INT24E R R R W R W R W R W R W R W Initial value 00H INT29E Enable or disable External Interrupt 5 0 Disable 1 Enable INT28E Enable or disable External Interrupt 4 0 Disable 1 Enable INT...

Page 72: ...alue 00H IP1 Interrupt Priority Register 1 F8H 7 6 5 4 3 2 1 0 IP17 IP16 IP15 IP14 IP13 IP12 IP11 IP10 R W R W R W R W R W R W R W R W Initial value 00H IP 7 0 IP1 7 0 Select Interrupt Group Priority...

Page 73: ...cording to EIEDGE External interrupt polarity register has a different means If EIEDGE is level type external interrupt polarity is able to have Low High level value If EIEGDE is edge type external in...

Page 74: ...and open the XOUT pin The default system clock is INT RC Oscillator and the default division rate is one In order to stabilize system internally use 1MHz RING oscillator for BIT WDT and ports de boun...

Page 75: ...DIV 1 0 When using fINTRC as system clock determine division rate Note when using fINTRC as system clock only division rate come into effect Note To change by software CBYS set to 1 DIV1 DIV0 descrip...

Page 76: ...be set 1 to use bypass control PLL VCO would not stop in the case of PLLCKS is 0 32KHz In addition this bit automatically set by interrupt event on sub active or power down 0 PLL output is Fvcoin 32...

Page 77: ...lly enable in sub active mode and has only 1mA current capability while main VDC for normal operation is off Second if user wanted to use 32 768KHz on PLL enable CS 1 0 0x2 of SCCR PLLCKS 0 and PLLEN...

Page 78: ...es a stable clock generation time On exiting Stop mode BIT gives a stable clock generation time As clock function time interrupt occurrence 11 2 2 Block Diagram RING OSC 1MHz BITR 8 bit COUNT BIT_CLK...

Page 79: ...BCK1 BCK0 R W R R R R W R W R W R W Initial value 05H BITF When BIT Interrupt occurs this bit becomes 1 For clearing bit write 0 to this bit 0 no generation 1 generation BCLR If BCLR Bit is written t...

Page 80: ...binary counter and the watchdog timer data register When the value of 8 bit binary counter is equal to the 8 bits of WDTR the interrupt request flag is generated This can be used as Watchdog timer int...

Page 81: ...ration the data should be greater than 01H WDTCR Watch Dog Timer Counter Register Read Case 8EH 7 6 5 4 3 2 1 0 WDTCR7 WDTCR6 WDTCR5 WDTCR4 WDTCR3 WDTCR2 WDTCR1 WDTCR0 R R R R R R R R Initial value 00...

Page 82: ...1 3 6 WDT Interrupt Timing Waveform Figure 11 4 WDT Interrupt Timing Waveform Source Clock BIT Overflow WDTCR 7 0 WDTR 7 0 WDTIF Interrupt WDTRESETB WDTCL Occur WDTR 0000_0011b Match Detect Counter Cl...

Page 83: ...be composed of 21 bit counter which is low 14 bit with binary counter and high 7 bit with auto reload counter in order to raise resolution In WTR it can control WT clear and set Interval value at writ...

Page 84: ...tial value 00H WTEN Control Watch Timer 0 disable 1 enable WTIFR When WT Interrupt occurs this bit becomes 1 For clearing bit write 0 to this bit or auto clear by INT_ACK signal 0 WT Interrupt no gene...

Page 85: ...WT period WT Interrupt Interval fwck 2 14 x 7bit WT Value 1 Note To guarantee proper operation it is greater than 01H to write WTR WTCR Watch Timer Counter Register Read Case 9EH 7 6 5 4 3 2 1 0 WTCR...

Page 86: ...l clock source external EC0 The clock source is selected by clock select logic which is controlled by the clock select T0CK 2 0 T1CK 1 0 TIMER0 clock source fX 2 4 16 64 256 1024 4096 EC0 TIMER1 clock...

Page 87: ...identical in Timer 0 1 the interrupt of timer P2 3 occurs The external clock EC0 counts up the timer at the rising edge If EC0 is selected from T0CK 2 0 EC0 port becomes input port The timer 1 can t u...

Page 88: ...3 4 5 6 n 2 n 1 n Interrupt Period PCP x n 1 0 Count Pulse Period PCP Up count Match with T0DR T1DR Occur Interrupt Occur Interrupt Occur Interrupt T0DR T1DR Value TIME STOP Timer 0 1 T0IF T1IF Interr...

Page 89: ...terrupt occurs at T0 1 and T0DR T1DR matching time respectively The capture result is loaded into CDR0 CDR1 The T0 T1 value is automatically cleared by hardware and restarts counter This timer interru...

Page 90: ...0 2 INT0 EIEDGE 0 B5H INT1IF INT1 Interrupt 8 bit Timer1 Counter T1 8Bit 8 bit Timer1 Data Register T1CN Clear B6H T1ST INT1 EIEDGE 1 POL1 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST T0EN T0PE CAP0 T0CK2...

Page 91: ...ture Mode T0 T1 Value Interrupt Request INT0F INT1F TIME 1 2 3 4 5 6 n 2 n 1 n Interrupt Interval Period 0 Count Pulse Period PCP Up count CDR0 CDR1 Load Ext INT0 1PIN T0 T1 Interrupt Request INT0F IN...

Page 92: ...utput by set T1_PE to 1 The period of the PWM output is determined by the T1PPR PWM period register T1PWHR 3 2 T1PWHR 1 0 PWM Period T1PWHR 3 2 T1PPR X Source Clock PWM Duty T1PWHR 1 0 T1PDR X Source...

Page 93: ...d if the duty value is set to 00H the PWM output is determined by the bit POL 1 Low 0 High PWM output is not retain high or low but toggle Figure 11 14 PWM Mode P r e s c a l e r MUX T0 Clock Source f...

Page 94: ...250ns 256us 3 9kHz T1PPR 8 Bit T1PDR 8 Bit PW1H3 PW1H2 PW1H1 PW1H0 1 1 FFH 0 0 80H T1CR 1 0 00H fXIN T1PWHR 03H T1PPR FFH T1PDR 80H T3 00 01 02 03 04 T1 PWM1 POL 1 T1CR 1 0 10H 2us T1PWHR 00H T1PPR 0E...

Page 95: ...imer 1 PWM Period Register T1 B6 R 00H Timer 1 Register T1PDR B6 R W 00H Timer 1 PWM Duty Register CDR1 B6 R 00H Capture 1 Data Register T1PWHR B7 W 00H Timer 1 PWM High Register 11 5 1 9 Timer Counte...

Page 96: ...fx 4096 1 1 1 External Clock EC0 T0CN Control Timer 0 Count pause continue 0 Temporary count stop 1 Continue count T0ST Control Timer 0 start stop 0 Counter stop 1 Clear counter and start T0 Timer 0...

Page 97: ...T1CK 1 0 Select clock source of Timer 1 Fx is the frequency of main system T1CK1 T1CK0 description 0 0 fx 0 1 fx 2 1 0 fx 16 1 1 Use Timer 0 Clock T1CN Control Timer 1 Count pause continue 0 Temporary...

Page 98: ...only write when PWM1E 1 CDR1 Capture 1 Data Register Read Case B6H 7 6 5 4 3 2 1 0 CDR17 CDR16 CDR15 CDR14 CDR13 CDR12 CDR11 CDR10 R R R R R R R R Initial value 00H CDR3 7 0 T1 Capture data T1PWHR Ti...

Page 99: ...ve the frequency is following 1 Value Prescaler 2 Frequency Clock Timer TxDR COMP f fCOMP is timer output frequency and TxDR is the 16 bits value of TxDRH and TxDRL To export the compare output as Tx...

Page 100: ...The PWMxLDR TxL CDRxL has the same function P R E S C A L E R 1 4 8 16 64 256 1024 2048 MUX TxH 8 bit TxL 8 bit 16 bit Counter TxST TxEN 4 ECTN TxCK 2 0 fX INTx EIEDGE 5 2 clear INTxIF INTx Interrupt...

Page 101: ...the PWM output is determined by the bit POL 1 High 0 Low And if the duty value is set to 00H the PWM output is determined by the bit POL 1 Low 0 High P R E S C A L E R 1 4 8 16 64 256 1024 2048 MUX Tx...

Page 102: ...2 Data Register High PWM2HPR BFH W FFH PWM 2 Period High Data Register T3CR C2H R W 00H Timer 3 Mode Control Register T3CR1 C3H R W 00H Timer 3 Mode Control Register 1 T3L C4H R 00H Timer 3 Low Regis...

Page 103: ...5 Capture Data Low Register T5H 2F3BH R 00H Timer 5 High Register PWM5HDR 2F3BH R W 00H PWM 5 Duty High Register CDR5H 2F3BH R 00H Timer 5 Capture Data High Register T5DRL 2F3CH W FFH Timer 5 Data Reg...

Page 104: ...elect clock source of Timer X Fx is the frequency of main system TxCK2 TxCK1 TxCK0 description 0 0 0 fX 0 0 1 fX 4 0 1 0 fX 8 0 1 1 fX 16 1 0 0 fX 64 1 0 1 fX 256 1 1 0 fX 1024 1 1 1 fX 2048 TxCN Cont...

Page 105: ...R R Initial value 00H CDRxL 7 0 Tx Capture Low data PWM2LDR PWM3LDR PWM4LDR PWM5LDR PWM 2 5 Low Duty Register Write Case BCH C4H CCH 2F3AH 7 6 5 4 3 2 1 0 PWMxLD7 PWMxLD6 PWMxLD5 PWMxLD4 PWMxLD3 PWMx...

Page 106: ...PWM2LPR PWM3LPR PWM4LPR PWM5LPR PWM 2 5 Low Period Register Write Case BEH C6H CEH 2F3CH 7 6 5 4 3 2 1 0 PWMxLP7 PWMxLP6 PWMxLP5 PWMxLP4 PWMxLP3 PWMxLP2 PWMxLP1 PWMxLP0 W W W W W W W W Initial value F...

Page 107: ...terrupt flag TMIF3 Timer 3 Interrupt Flag 0 No Timer 3 interrupt 1 Timer 3 interrupt occurred write 1 to clear interrupt flag TMIF2 Timer 2 Interrupt Flag 0 No Timer 2 interrupt 1 Timer 2 interrupt oc...

Page 108: ...ZDR 7 0 Buzzer Frequency kHz BUZCR 2 1 00 BUZCR 2 1 01 BUZCR 2 1 10 BUZCR 2 1 11 0000_0000 125kHz 62 5kHz 31 25kHz 15 625kHz 0000_0001 62 5kHz 31 25kHz 15 625kHz 7 812kHz 1111_1101 492 126Hz 246 063Hz...

Page 109: ...UZDR Buzzer Data Register 8FH 7 6 5 4 3 2 1 0 BUZDR7 BUZDR6 BUZDR5 BUZDR4 BUZDR3 BUZDR2 BUZDR1 BUZDR0 R W R W R W R W R W R W R W R W Initial value FFH BUZDR 7 0 This bits control the Buzzer frequency...

Page 110: ...and RX Complete Double Speed Asynchronous Communication Mode USART has three main parts of Clock Generator Transmitter and Receiver The Clock Generation logic consists of synchronization logic for ex...

Page 111: ...ontrol RXC TXC UMSEL1 UMSEL0 UPM1 UPM0 USIZE2 USIZE1 USIZE0 UCPOL UCTRLx1 ADDRESS E2H FAH 2F28H 2F30H INITIAL VALUE 0000_0000B UDRIE TXCIE RXCIE WAKEIE TXE RXE USARTEN U2X UCTRLx2 ADDRESS E3H FBH 2F29...

Page 112: ...d mode is controlled by the U2X bit in the UCTRLx2 register The MASTER bit in UCTRLx2 register controls whether the clock source is internal Master mode output port or external Slave mode input port T...

Page 113: ...frequency of main system clock SCLK 11 7 5 Synchronous mode Operation When synchronous or spi mode is used the XCK pin will be used as either clock input slave or clock output master The dependency b...

Page 114: ...y followed by a new frame or the communication line can be set to an idle state The idle means high state of data pin The next figure shows the possible combinations of the frame formats Bits inside b...

Page 115: ...rol registers If the 9 bit characters are used in asynchronous or synchronous operation mode USIZE 2 0 7 the ninth bit must be written to the TX8 bit in UCTRLx3 register before loading transmit buffer...

Page 116: ...tion mode the Receiver starts data reception when it detects a valid start bit LOW on RXD pin Each bit after start bit is sampled at pre defined baud rate asynchronous or sampling edge of XCK synchron...

Page 117: ...e buffer had a Parity Error when received If Parity Check function is not enabled UPM 1 0 the PE bit is always read zero Note The error flags related to receive operation are not used when USART is in...

Page 118: ...mal mode samples 4 5 and 6 for Double Speed mode If more than 2 samples have low levels the received bit is considered to a logic 0 and more than 2 samples have high levels the received bit is conside...

Page 119: ...other SPI devices 11 7 10 1 SPI Clock formats and timing To accommodate a wide variety of synchronous serial peripherals from different manufacturers the USART has a clock polarity bit UCPOL and a cl...

Page 120: ...puts respectively At the second XCK edge the USART shifts the second data bit value out to the MOSI and MISO outputs of the master and slave respectively Unlike the case of UCPHA 1 when UCPHA 0 the sl...

Page 121: ...reuses the USART resources SPI mode of operation is similar to that of synchronous or asynchronous operation An SPI transfer is initiated by checking for the USART Data Register Empty flag UDRE 1 and...

Page 122: ...R W 00H USART Control 3 Register 3 USTAT3 2F33H R 80H USART Status Register 3 UBAUD3 2F34H R W FFH USART Baud Rate Generation Register 3 UDATA3 2F35H R W FFH USART Data Register 3 11 7 12 USART Regist...

Page 123: ...edge and trailing edge means 2nd or last clock edge of XCK in one XCK pulse And Sample means detecting of incoming receive bit Setup means preparing transmit data UCPOL UCPHA Leading Edge Trailing Edg...

Page 124: ...on and XCK is input pin 1 Master mode operation and XCK is output pin LOOPS Controls the Loop Back mode of USART for test mode 0 Normal operation 1 Loop Back mode DISXCK In Synchronous mode of operati...

Page 125: ...There is no data unread in the receive buffer 1 There are more than 1 data in the receive buffer WAKE This flag is set when the RX pin is detected low while the CPU is in stop mode This flag can be u...

Page 126: ...nd do not write 0 or 1 in synchronous or spi mode UDATAx USART Data Register E7H FFH 2F2DH 2F34H 7 6 5 4 3 2 1 0 UDATA7 UDATA6 UDATA5 UDATA4 UDATA3 UDATA2 UDATA1 UDATA0 R W R W R W R W R W R W R W R W...

Page 127: ...95 0 0 191 0 0 9600 23 0 0 47 0 0 25 0 2 51 0 2 47 0 0 95 0 0 14 4K 15 0 0 31 0 0 16 2 1 34 0 8 31 0 0 63 0 0 19 2K 11 0 0 23 0 0 12 0 2 25 0 2 23 0 0 47 0 0 28 8K 7 0 0 15 0 0 8 3 5 16 2 1 15 0 0 31...

Page 128: ...SB first data transfer or MSB first data transfer 11 8 2 Block Diagram Figure 11 31 SPI Block Diagram 64 32 P r e s c a l e r MUX 2 4 8 16 fSCLK PxDA x SPICR 2 0 3 MUX Edge Detector SPI Control Circui...

Page 129: ...only either transmit or receive clear the TXENA or RXENA In this case user can use disabled pin by GPIO freely 11 8 4 SS pin function 1 When the SPI is configured as a Slave the SS pin is always input...

Page 130: ...R W 0H SPI Control Register 0 SPIDR0 D3H R W 0H SPI Data Register 0 SPISR0 D4H 0H SPI Status Register 0 SPICR1 92H R W 0H SPI Control Register 1 SPIDR1 93H R W 0H SPI Data Register 1 SPISR1 F1H 0H SPI...

Page 131: ...0 Slave mode 1 Master mode CPOL CPHA These two bits control the serial clock SCK mode Clock Polarity CPOL bit determine SCK s value at idle mode Clock Phase CPHA bit determine if data is sampled on t...

Page 132: ...rupt is disable TCIR bit is cleared when user read the status register SPISR and then access read write the data register SPIDR 0 Interrupt cleared 1 Transmission Complete and Interrupt Requested WCOL...

Page 133: ...ure 11 34 I2 C Block Diagram 11 9 3 I2 C Bit Transfer The data on the SDA line must be stable during HIGH period of the clock SCL The HIGH or LOW state of the data line can only change when the clock...

Page 134: ...is busy between START and STOP condition If a repeated START condition Sr is generated instead of STOP condition the bus stays busy So the START and repeated START conditions are functionally identica...

Page 135: ...t signal the end of data to the slave transmitter by not generating an acknowledge on the last byte that was clocked out of the slave The slave transmitter must release the data line to allow the mast...

Page 136: ...ecause the level on the bus doesn t correspond to its own level Arbitration continues for many bits until a winning master gets the ownership of I2C bus Its first stage is comparison of the address bi...

Page 137: ...slave acknowledged or not in the 9th high period of SCL If the master gains bus mastership I2C generates GCALL interrupt regardless of the reception of ACK from the slave device When I2C loses bus mas...

Page 138: ...et the STOP bit in I2CMR 3 Master transmits repeated START condition with not checking ACK signal In this case load SLA R W into the I2CDR and set the START bit in I2CMR After doing one of the actions...

Page 139: ...te From slave to master 0xxx Value of Status Register ACK Interrupt SCL line is held low Interrupt after stop command P Arbitration lost as master and addressed as slave LOST Other master continues Sl...

Page 140: ...e I2C operates as a slave transmitter or a slave receiver go to appropriate section In this stage I2C holds the SCL LOW This is because to decide whether I2C continues serial transfer or stops communi...

Page 141: ...P interrupt The STOP bit indicates that data transfer between master and slave is over To clear I2CSR write arbitrary value to I2CSR After this I2C enters idle state The processes described above for...

Page 142: ...dition Else if the address equals to SLA bits and the ACKEN bit is enabled I2C generates SSEL interrupt and the SCL line is held LOW Note that even if the address equals to SLA bits when the ACKEN bit...

Page 143: ...hold time of SDA is calculated by SDAH x period of SCLK where SDAH is multiple of number of SCLK coming from I2CSDAHR When the hold time of SDA is longer than the period of SCLK I2C slave cannot tran...

Page 144: ...is being received 6 In this step I2C generates TEND interrupt and holds the SCL line LOW regardless of the reception of ACK signal from master Slave can select one of the following cases 1 No ACK sign...

Page 145: ...r I2CSDAHR DEH R W 01H SDA Hold Time Register I2CDR DFH R W FFH I2 C Data Register I2CSAR D7H R W 00H I2 C Slave Address Register I2CSAR1 D6H R W 00H I2 C Slave Address Register 1 SLA W ACK DATA LOST...

Page 146: ...e 1 I2 C is active RESET Initialize internal registers of I2 C 0 No operation 1 Initialize I2 C auto cleared INTEN Enable interrupt generation of I2 C 0 Disable interrupt operates in polling mode 1 En...

Page 147: ...d SSEL This bit is set when I2 C is addressed by other master Note 1 0 I2 C is not selected as slave 1 I2 C is addressed by other master and acts as a slave MLOST This bit represents the result of bus...

Page 148: ...R W R W R W R W R W R W R W Initial value 01H SDAH 7 0 This register is used to control SDA output timing from the falling edge of SCL Note that SDA is changed after tSCLK SDAH In master mode load ha...

Page 149: ...I2 C Slave Address Register 1 D6H 7 6 5 4 3 2 1 0 SLA7 SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 GCALLEN R W R W R W R W R W R W R W R W Initial value 00H SLA 7 1 These bits configure the slave address of this I...

Page 150: ...ADCLR contains the results of the A D conversion When the conversion is completed the result is loaded into the ADCHR and ADCLR the A D conversion status bit AFLAG is set to 1 and the A D interrupt is...

Page 151: ...nnecting Capacitor Align bit set 0 ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 ADCRH7 ADCRH6 ADCRH5 ADCRH4 ADCRH3 ADCRH2 ADCRH1 ADCRH0 ADCRL7 ADCRL6 ADCRL5 ADCRL4 ADCRH 7...

Page 152: ...consists of A D Converter Mode Register ADCM A D Converter Result High Register ADCRH A D Converter Result Low Register ADCRL A D Converter Mode 2 Register ADCM2 Note when STBY bit is set to 1 ADCM2...

Page 153: ...verter operation state 0 During A D Conversion 1 A D Conversion finished ADSEL 3 0 A D Converter input selection ADSEL3 ADSEL 2 ADSEL 1 ADSEL 0 Description 0 0 0 0 Channel0 AN0 0 0 0 1 Channel1 AN1 0...

Page 154: ...0 A D Trigger Source selection TSEL2 TSEL1 TSEL0 Description 0 0 0 Ext Interrupt 0 0 0 1 Ext Interrupt 1 0 1 0 Pin Change Interrupt 7 0 1 1 Timer0 interrupt event 1 0 0 Timer1 interrupt event 1 0 1 T...

Page 155: ...is replaced with the dividend value The registers for CALCULATOR_AI can be indirectly accessed via CAL_CNTR CAL_ADDR CAL_DATA to save the SFR area and to increase the code performance The access addr...

Page 156: ...red after one clock cycle 0 Idle 1 Start of Division auto cleared CAL_ADDR Calculator Control Register EH 7 6 5 4 3 2 1 0 CAL_ADDR7 CAL_ADDR6 CAL_ADDR5 CAL_ADDR4 CAL_ADDR3 CAL_ADDR2 CAL_ADDR1 CAL_ADDR...

Page 157: ...5 08 ADDR ADDR 1 CAL_DATA a MA 07 00 a 07 00 ADDR ADDR 1 CAL_DATA b 8 MB 15 08 b 15 08 ADDR ADDR 1 CAL_DATA b MB 07 00 b 07 00 ADDR ADDR 1 now ADDR points to MO 31 24 so just read it mul_o unsigned lo...

Page 158: ...R ADDR 1 CAL_DATA b 8 DB 15 08 b 15 08 ADDR ADDR 1 CAL_DATA b DB 07 00 b 07 00 ADDR ADDR 1 while CAL_CNTR CAL_DIV_DONE 0 wait until division is done need 32clock cycles now ADDR points to DQ 31 24 so...

Page 159: ...ck mode Stop Only operate in sub clock mode Timer Operates Continuously Halted Only when the Event Counter Mode is Enable Timer operates Normally Halted Only when the Event Counter Mode is Enable Time...

Page 160: ...ease Timing by RESET Ex MOV PCON 0000_0001b setting of IDLE mode set the bit of STOP and IDLE Control register PCON 12 4 STOP mode The power control register is set to 03h to enter the STOP Mode In th...

Page 161: ...this guarantees that oscillator has started and stabilized Figure 12 3 STOP Mode Release Timing by External Interrupt Figure 12 4 STOP Mode Release Timing by RESET OSC CPU Clock RESETB Normal Operati...

Page 162: ...igure 12 5 Interrupt Enable Flag of All EA of IE should be set to 1 Released by only interrupt which each interrupt enable flag 1 and jump to the relevant interrupt service routine Figure 12 5 STOP1 2...

Page 163: ...5 4 3 2 1 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R W R W R W R W R W R W R W R W Initial value 00H IDLE Mode 01H IDLE mode enable STOP1 2 Mode 03H STOP1 2 mode enable Note 1 To enter IDLE mode PCO...

Page 164: ...RESETB Power ON RESET POR WDT Overflow Reset In the case of WDTEN 1 BOD Reset In the case of BODEN 1 OCD Reset 13 3 Block Diagram Figure 13 1 RESET Block Diagram On Chip Hardware Initial Value Program...

Page 165: ...Figure 13 2 Reset noise canceller time diagram 13 5 Power ON RESET When rising device power the POR Power ON Reset have a function to reset the device If using POR it executes the device RESET functi...

Page 166: ...32 INT OSC 128KHz RESET_SYSB Config Read 250us X 30h about 12ms 250us X 40h about 16ms 00 01 02 03 04 05 06 00 01 02 03 00 01 02 2F 30 F1 3F 40 00 01 02 03 Ext_reset have not an effect on counter valu...

Page 167: ...must rise over than flash operating voltage for Config read Slew Rate 0 025V ms Config read point about 1 5V 1 6V Config Value is determined by Writing Option Rising section to Reset Release Level 16m...

Page 168: ...with 16ms and after the stable state the internal RESET becomes 1 The Reset process step needs 5 oscillator clocks And the program execution starts at the vector address stored at address 0000H Figure...

Page 169: ...In the STOP mode this will contribute significantly to the total current consumption So to minimize the current consumption the BODEN bit is set to off by software Figure 13 9 Block Diagram of BOD Fi...

Page 170: ...D Control Register BODR 13 7 3 Register description for Reset Operation BODR BOD Control Register 86H 7 6 5 4 3 2 1 0 PORF EXTRF WDTRF OCDRF BODRF BODLS 1 BODLS 0 BODEN R W R W R W R W R W R W R W R W...

Page 171: ...g bit The bit is reset by writing 0 to this bit or by Power ON reset 0 No detection 1 Detection OCDRF On Chip Debug Reset flag bit The bit is reset by writing 0 to this bit or by Power ON reset 0 No d...

Page 172: ...chip Debug system 14 1 2 Feature Two wire external interface 1 wire serial clock input 1 wire bi directional serial data bus Debugger Access to All Internal Peripheral Units Internal data RAM Program...

Page 173: ...s parity has no error When transmitter has no acknowledge Acknowledge bit is 1 at tenth clock error process is executed in transmitter When acknowledge error is generated host PC makes stop condition...

Page 174: ...bit transmission packet 14 2 2 Packet transmission timing 14 2 2 1 Data transfer Figure 14 3 Data transfer on the twin bus St Sp START STOP DSDA DSCL LSB acknowledgement signal from receiver ACK ACK...

Page 175: ...stop condition 14 2 2 4 Acknowledge bit Figure 14 6 Acknowledge on the serial bus 1 9 2 10 Data output by transmitter Data output By receiver DSCL from master clock pulse for acknowledgement no acknow...

Page 176: ...ugger Serial Clock Line DSDA Debugger Serial Data Line DSDA OUT DSDA IN Host Machine Master Target Device Slave VDD VDD Current source for DSCL to fast 0 to 1 transition in high speed mode pull up res...

Page 177: ...re 15 2 Flash and EEPROM Control and status register Registers to control Flash and Data EEPROM are Mode Register FEMR Control Register FECR Status Register FESR Time Control Register FETCR Address Lo...

Page 178: ...fer 1 Select page buffer OTPE Select OTP area instead of program memory 0 Deselect OTP area 1 Select OTP area VFY Set program or erase verify mode with PGM or ERASE Program Verify PGM 1 VFY 1 Erase Ve...

Page 179: ...set 1 0 Write checksum reset WRITE and READ bits can be used in program erase and verify mode with FEAR registers Read or writes for memory cell or page buffer uses read and write enable signals from...

Page 180: ...ame least significant bits as the number of bits of page address In auto verify mode address increases automatically by one FEARs are write only register Reading these registers returns 24 bit checksu...

Page 181: ...128 3 2768ms In the case of 10 of error rate of counter source clock program or erase time is 3 0 3 5ms Program erase time calculation for page write or erase Tpe TCON 1 2 SCLK 128 for bulk erase Tbe...

Page 182: ...and written by byte or page One page is 16 byte It is mapped to external data memory of 8051 Figure 15 3 Data EEPROM memory map Data EEPROM 4K Bytes XDATA Memory 3000h FFFFh D P T R F E A R L MUX pgm...

Page 183: ...Aug 02 2018 Ver 2 9 183 Figure 15 4 Address configuration of data EEPROM 11 10 9 8 7 6 5 4 3 2 1 0 PAGE ADDRESS WORD ADDRESS Data Memory 0xF 0x0 0x00 0xFF Page buffer size 16Bytes Page 255 Page 254 Pa...

Page 184: ...FEMR 4 1 FEMR 5 1 FEMR 2 FECR 6 FECR 7 ERASE VFY PGM VFY OTPE AEE AEF Figure 15 5 The sequence of page program and erase of Flash memory Page Buffer Reset Page Buffer Load 0X00H Erase Erase Latency 50...

Page 185: ...uest debug mode Step 4 Read data from Flash 15 4 1 2 Enable program mode Step 1 Enter OCD ISP mode 1 Step 2 Set ENBDM bit of BCR Step 3 Enable debug and Request debug mode Step 4 Enter program erase m...

Page 186: ...operation Step 10 Read FESR until PEVBSY is 1 Step 11 Repeat step2 to step 8 until all pages are written 15 4 1 4 Flash page erase mode Step 1 Enable program mode Step 2 Reset page buffer FEMR 1000_0...

Page 187: ...elect page buffer FEMR 1000_1001 Step 4 Write data to page buffer Address automatically increases by twin Step 5 Set write mode and select OTP area FEMR 1010_0101 Step 6 Set page address FEARH FEARM F...

Page 188: ...ffer read Step 1 Enable program mode Step 2 Select page buffer FEMR 1000_1001 Step 3 Read data from Flash 15 4 2 Data EEPROM operation Program and erase operation of Data EEPROM are executed by direct...

Page 189: ...Read FESR until PEVBSY is 1 Step 11 Repeat step2 to step 8 until all pages are written 15 4 2 4 EEPROM page erase mode Step 1 Enable program mode Step 2 Reset page buffer FEMR 0100_0001 FECR 0000_0010...

Page 190: ...h and Data EEPROM Program Erase Mode Table 15 3 Operation Mode Operation mode Description F L A S H Flash read Read cell by byte Flash write Write cell by bytes or page Flash page erase Erase cell by...

Page 191: ...memory type Address auto increment is supported when read or write data without address Figure 15 7 Pin diagram for parallel programming Table 15 4 The selection of memory type by ADDRH 7 4 ADDRH 7 4...

Page 192: ...nRD H H L H H H H H H H H H H H PDATA ADDRL DATA0 DATA1 DATA2 DATA3 DATAn n byte data write with 1 byte address nALE L H H H H H H nWR L H L H L H L H L H L H L H nRD H H H H H H H H H H H H H H PDAT...

Page 193: ...AM A0H AL 00H AL 01H Write 0x02 0x0A001 Write Write Write Write Write Write Write Write TAS TAH TWE Read address auto increment AH 00H Write AL AM AH Data AL AM Data AL Data Out Data 1 byte write wit...

Page 194: ...5 6 2 Mode entrance of Byte parallel TARGET MODE P0 3 0 P0 3 0 P0 3 0 Byte Parallel Mode 4 h5 4 hA 4 h5 Figure 15 11 Byte parallel mode Power on reset nTEST DSDA R0 3 0 RESET_SYSB h5 hA h5 Release fro...

Page 195: ...DATA EEPROM OTP FLASH DATA EEPROM OTP LOC KE LOC KF R W P E B E R W P E B E R W P E B E R W P E B E R W P E B E R W P E B E 0 0 O X X X O O O O X X X X O O O O O O O O O O O O 0 1 O X X X O O O O X X...

Page 196: ...SXINEN Enable External Sub Oscillator 0 Sub OSC disable default 1 Sub OSC enable XINENA Enable External Main Oscillator 0 Main OSC disable default 1 Main OSC enable OCDSEL Selects noise cancelling sch...

Page 197: ...with borrow 1 1 96 97 SUBB A data Subtract immediate from A with borrow 2 1 94 INC A Increment A 1 1 04 INC Rn Increment register 1 1 08 0F INC dir Increment direct byte 2 1 05 INC Ri Increment indir...

Page 198: ...rect byte 2 2 88 8F MOV dir dir Move direct byte to direct byte 3 2 85 MOV dir Ri Move indirect memory to direct byte 2 2 86 87 MOV dir data Move immediate to direct byte 3 2 75 MOV Ri A Move A to ind...

Page 199: ...60 JNZ rel Jump on accumulator 0 2 2 70 CJNE A dir rel Compare A direct jne relative 3 2 B5 CJNE A d rel Compare A immediate jne relative 3 2 B4 CJNE Rn d rel Compare register immediate jne relative...

Page 200: ...th input port it could cause error due to the timing conflict inside the MCU Compare jump Instructions which cause potential error used with input port condition JB bit rel jump on direct bit 1 JNB bi...

Page 201: ...port use internal parameter MOV 020 0 C move JB 020 0 xxx compare SETB 088 0 SJMP yyy xxx CLR 088 0 yyy MOV C 088 1 CPL C MOV 088 1 C SJMP zzz bit tt while 1 tt P00 if tt 0 P10 1 else P10 0 P11 1 zzz...