MC96F6432
June 22, 2018 Ver. 2.9
205
The process for detecting stop bit is like clock and data recovery process. That is, if 2 or more samples of 3
center values have high level, correct stop bit is detected, else a frame error (FE0) flag is set. After deciding
whether the first stop bit is valid or not, the Receiver goes to idle state and monitors the RXD0 line to check a
valid high to low transition is detected (start bit detection).
Figure 11.63 Stop Bit Sampling and Next Start Bit Sampling (USI0)
RXD0
1
2
3
4
5
6
7
8
9
10
11
12
13
STOP 1
1
2
3
4
5
6
7
Sample
(DBLS0 = 0)
Sample
(DBLS0 = 1)
(A)
(B)
(C)
Summary of Contents for MC96F6432 Series
Page 24: ...MC96F6432 24 June 22 2018 Ver 2 9 4 Package Diagram Figure 4 1 48 Pin LQFP 0707 Package...
Page 25: ...MC96F6432 June 22 2018 Ver 2 9 25 Figure 4 2 44 Pin MQFP Package...
Page 26: ...MC96F6432 26 June 22 2018 Ver 2 9 Figure 4 3 32 Pin LQFP Package...
Page 27: ...MC96F6432 June 22 2018 Ver 2 9 27 Figure 4 4 32 Pin SOP Package...
Page 28: ...MC96F6432 28 June 22 2018 Ver 2 9 Figure 4 5 28 Pin SOP Package...
