MC96F6432
236
June 22, 2018 Ver. 2.9
11.13.5 USI1 External Clock (SCK1)
External clocking is used in the synchronous mode of operation.
External clock input from the SCK1 pin is sampled by a synchronization logic to remove meta-stability. The
output from the synchronization logic must be passed through an edge detector before it is used by the
transmitter and receiver. This process introduces two CPU clock period delay. The maximum frequency of the
external SCK1 pin is limited up-to 1MHz.
11.13.6 USI1 Synchronous mode operation
When synchronous or SPI mode is used, the SCK1 pin will be used as either clock input (slave) or clock output
(master).
Data sampling and transmitter is issued on the different edge of SCK1 clock each other. For example, if
data input on RXD1 (MISO1 in SPI mode) pin is sampled on the rising edge of SCK1 clock, data output on TXD1
(MOSI1 in SPI mode) pin is altered on the falling edge.
The CPOL1 bit in USI1CR1 register selects which SCK1 clock edge is used for data sampling and which is used
for data change. As shown in the figure below, when CPOL1 is zero, the data will be changed at rising SCK1
edge and sampled at falling SCK1 edge.
Figure 11.80 Synchronous Mode SCK1 Timing (USI1)
SCK1
TXD1/RXD1
CPOL1 = 1
TXD1/RXD1
SCK1
CPOL1 = 0
Sample
Sample
Summary of Contents for MC96F6432 Series
Page 24: ...MC96F6432 24 June 22 2018 Ver 2 9 4 Package Diagram Figure 4 1 48 Pin LQFP 0707 Package...
Page 25: ...MC96F6432 June 22 2018 Ver 2 9 25 Figure 4 2 44 Pin MQFP Package...
Page 26: ...MC96F6432 26 June 22 2018 Ver 2 9 Figure 4 3 32 Pin LQFP Package...
Page 27: ...MC96F6432 June 22 2018 Ver 2 9 27 Figure 4 4 32 Pin SOP Package...
Page 28: ...MC96F6432 28 June 22 2018 Ver 2 9 Figure 4 5 28 Pin SOP Package...
