MC96FM204/FM214
April 7, 2016 Ver. 1.8
69
10.6 Effective Timing after Controlling Interrupt Bit
Case a) Control Interrupt Enable Register (IE, IE1, IE2, IE3)
Figure 10.4 Effective Timing of Interrupt Enable Register
Case b) Interrupt flag Register
Figure 10.5 Effective Timing of Interrupt Flag Register
Interrupt Flag Register
Command
Next Instruction
Next Instruction
After executing next instruction,
interrupt flag result is effective.
Interrupt Enable Register
command
Next Instruction
Next Instruction
After executing IE set/clear, enable
register is effective.
Summary of Contents for MC96FM204
Page 17: ...MC96FM204 FM214 April 7 2016 Ver 1 8 17 4 Package Diagram Figure 4 1 20 Pin SOP Package ...
Page 18: ...MC96FM204 FM214 18 April 7 2016 Ver 1 8 Figure 4 2 20 Pin TSSOP Package ...
Page 19: ...MC96FM204 FM214 April 7 2016 Ver 1 8 19 Figure 4 3 16 Pin SOP Package ...
Page 20: ...MC96FM204 FM214 20 April 7 2016 Ver 1 8 Figure 4 4 16 Pin TSSOP Package ...