10. Timer0/1/2/3
MC97F6108A User’s manual
92
PWMxDRL (PWM0/1/2/3 Duty Register Low, Write Case) : B4H, BCH, C4H, CCH
7
6
5
4
3
2
1
0
PWMxDRL7 PWMxDRL6 PWMxDRL5 PWMxDRL4 PWMxDRL3 PWMxDRL2
PWMxDRL1 PWMxDRL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00
H
PWMxDRL[7:0]
Tx PWM Duty Low data
NOTE:
Reading and writing is possible only when PWMxE = 1 and TxST = 0
TxH (Timer0/1/2/3 Register High, Read Case) : B5H, BDH, C5H, CDH
7
6
5
4
3
2
1
0
TxH7
TxH6
TxH5
TxH4
TxH3
TxH2
TxH1
TxH0
R
R
R
R
R
R
R
R
Initial value: 00
H
TxH[7:0]
TxH Counter Period High data.
CDRxH (Capture0/1/2/3 Data High Register, Read Case) : B5H, BDH, C5H, CDH
7
6
5
4
3
2
1
0
CDRxH07
CDRxH06
CDRxH05
CDRxH04
CDRxH03
CDRxH02
CDRxH01
CDRxH00
R
R
R
R
R
R
R
R
Initial value: 00
H
CDRxH[7:0]
Tx Capture High data
PWMxDRH (PWM0/1/2/3 Duty Register High, Write Case) : B5H, BDH, C5H, CDH
7
6
5
4
3
2
1
0
PWMxDRH7 PWMxDRH6 PWMxDRH5 PWMxDRH4 PWMxDRH3 PWMxDRH2 PWMxDRH1 PWMxDRH0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00
H
PWMxDRH[7:0]
Tx PWM Duty High data
NOTE:
Reading and writing is effective only when PWMxE = 1 and TxST = 0
TxDRL (Timer0/1/2/3 Data Register Low, Write Case) : B6H, BEH, C6H, CEH
7
6
5
4
3
2
1
0
TxDRL7
TxDRL6
TxDRL5
TxDRL4
TxDRL3
TxDRL2
TxDRL1
TxDRL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: FF
H
TxDRL[7:0]
TxL Compare Low data
NOTE:
Be sure to clear PWMxE before loading this register
.
