Acces I/O products PCI-DA12-8/16, User Manual

Page 1: ...10623 Roselle Street San Diego CA 92121 858 550 9559 FAX 858 550 7322 contactus accesio com www accesio com MODEL PCI DA12 8 16 USER MANUAL FILE MPCI DA12 16 D1u ...

Page 2: ...ES nor the rights of others IBM PC PC XT and PC AT are registered trademarks of the International Business Machines Corporation Printed in USA Copyright 2001 2011 by ACCES I O Products Inc 10623 Roselle Street San Diego CA 92121 All rights reserved WARNING ALWAYS CONNECT AND DISCONNECT YOUR FIELD CABLING WITH THE COMPUTER POWER OFF ALWAYS TURN COMPUTER POWER OFF BEFORE INSTALLING A CARD CONNECTING...

Page 3: ...or parts not excluded by warranty Warranty commences with equipment shipment Following Years Throughout your equipment s lifetime ACCES stands ready to provide on site or in plant service at reasonable rates similar to those of other manufacturers in the industry Equipment Not Manufactured by ACCES Equipment provided but not manufactured by ACCES is warranted and will be repaired according to the ...

Page 4: ...g 15 Table 5 1 Register Map 16 Table 5 2 I O Address Map for the Digital I O and Counter Timers 17 Table 5 3 DAC Data Format 17 Table 5 4 I O Address Table for Digital 18 Table 5 5 Control Register Bit Assignments 18 Chapter 6 8254 Counter Timer 20 Chapter 7 Software 25 Chapter 8 Calibration 26 Chapter 9 Connector Pin Assignments 28 Table 9 1 P2 DAC Pin Assignments 28 Table 9 2 P3 Digital I O Coun...

Page 5: ...puts can be updated either independently simultaneously by command or simultaneously by timer The DAC outputs are undefined at power up Therefore in order to prevent excessive voltage output to external circuits the card contains automatic circuits that set D A outputs to less than 15 percent of span at system power on Upon power up the card is not in the Simultaneous Update mode After all DACs ha...

Page 6: ...or Current sink channels Current Sink Mode 4 to 20 mA with excitation voltage 8 36 VDC Voltages 15mA max 0V to 2 5V 0V to 5V 0V to 10V 2 5V to 2 5V 5V to 5V 10V to 10V AD7237 D A Converter Double Buffered Simultaneous Update Relative Accuracy LSB Monotonicity 12 bits over operating temperature range Settling Time 8 usec to one LSB for full scale step input Linearity LSB integral non linearity over...

Page 7: ...its Event Counter Range 16 bits Minimum Clock Pulse Width 30 ns high 50 ns low Environmental Operating Temperature Range 0 C to 60 C Storage Temperature Range 20 C to 85 C Humidity 5 to 95 non condensing External DAC Reference input 4 5V to 5 5V 5V Source output 0 to 500 mA fused resetting Size 12 2 long 310 mm Power Required 12 VDC at 310 mA maximum 16 channels 12 VDC at 150 mA maximum 5 VDC at 6...

Page 8: ...Manual PCI DA12 8 16 8 Figure 1 1 Block Diagram ...

Page 9: ... information on installing under Linux Installing from CD Perform the following steps as appropriate for your operating system Substitute the appropriate drive letter for your drive where you see D in the examples below Windows 1 Place the CD into your CD ROM drive 2 The system should automatically run the install program If the install program does not run promptly click START RUN and type click ...

Page 10: ...rd depending on the operating system and automatically finish installing the drivers 9 Run PCIfind exe to complete installing the card into the registry for Windows only and to determine the assigned resources 10 Run one of the provided sample programs that was copied to the newly created card directory from the CD to test and validate your installation The base address assigned by BIOS or the ope...

Page 11: ...og outputs are updated under program control in any of three ways a Automatic Update Each channel is updated individually when new data are written to the related high byte base address Individual update mode may be set by a special read operation as defined in the programming section of this manual b Simultaneous Update The outputs of all D As may be updated simultaneously This is done by first e...

Page 12: ...Manual PCI DA12 8 16 12 Figure 3 1 Option Selection Map S1 V P2 P3 V JP1 JP3 JP11 JP5 JP13 JP7 JP15 JP2 JP10 JP9 JP4 JP12 JP6 JP14 JP8 JP16 S9 S3 S11 S5 S13 S7 S15 S2 I I S10 S4 S12 S6 S14 S8 S16 ...

Page 13: ...Manual PCI DA12 8 16 13 Figure 3 2 Field Wiring Diagrams Caution Do not connect current loops in a DAC that is set to voltage mode The loop supply can destroy the DAC ...

Page 14: ...of the cards detected on the PCI bus the addresses assigned to each function on each of the cards and the respective IRQs Alternatively some operating systems can be queried to determine which resources were assigned In these operating systems you can use either PCIFind or the Device Manager utility from the System Properties Applet of the control panel The card is installed in the Data Acquisitio...

Page 15: ...r default mode of operation for the DAC card When a value is written to a DAC address the output does not change until an output update is commanded via a read from Base Address 8 Alternatively a read of Base Address A will update the DAC registers and switch the board to Automatic Update Mode While in Simultaneous Update Mode a single read will load all DAC registers with the value waiting in the...

Page 16: ... 3 High Byte Base 8 DAC 4 Low Byte Update all outputs and place card in Simultaneous Mode Base 9 DAC 4 High Byte Base A DAC 5 Low Byte Update all outputs and release card from Simultaneous Mode Base B DAC 5 High Byte Base C DAC 6 Low Byte Clear IRQ Base D DAC 6 High Byte Base E DAC 7 Low Byte Restrict Output Voltage Limits outputs to 15 of full scale range Base F DAC 7 High Byte Clear Restrict Out...

Page 17: ...r Timer Control Register Counter Timer Control Register Table 5 2 I O Address Map for the Digital I O and Counter Timers BIT D7 D6 D5 D4 D3 D2 D1 D0 Low Byte B7 B6 B5 B4 B3 B2 B1 B0 High Byte x x x x B11 B10 B9 B8 Table 5 3 DAC Data Format For Unipolar ranges For Unipolar ranges data are in true binary form XXXX 0000 0000 0000 Zero XXXX 1000 0000 0000 Scale XXXX 1111 1111 1111 Full Scale MSB or B1...

Page 18: ...Lo C0 C3 1 Input 0 Output D1 Port B 1 Input 0 Output D2 Mode Selection 1 Mode 1 0 Mode 0 D3 Port C Hi C4 C7 1 Input 0 Output D4 Port A 1 Input 0 Output D5 D6 Mode Selection 01 Mode 1 00 Mode 0 1X Mode 2 D7 Mode Set Flag Tristate 1 Active Tristate Table 5 5 Control Register Bit Assignments Note PPI Mode 1 cannot be used with this circuit without modification Thus bits D2 D5 and D6 should always be ...

Page 19: ...to be set as outputs you may set the values of the respective port with the outputs still in tristate condition Lastly to enable the ports a control byte with bit D7 low must be sent to Base Address 23 Note All data bits except D7 must be the same for the two control bytes Those buffers will now remain enabled until another control byte with data bit D7 high is sent to Base Address 23 ...

Page 20: ...trigger to begin the one shot pulse and goes high when the counter reaches zero Additional triggers result in reloading the count and starting the cycle over If a trigger occurs before the counter decrements to zero a new count is loaded This forms a retriggerable one shot In mode 1 a low output pulse is provided with a period equal to the counter count down time Mode 2 Rate Generator This mode pr...

Page 21: ...rol register The counters are programmed by writing a control byte into a counter control register at Base Address 27 The control byte specifies the counter to be programmed the counter mode the type of read write operation and the modulus The control byte format is as follows B7 B6 B5 B4 B3 B2 B1 B0 SC1 SC0 RW1 RW0 M2 M1 M0 BCD SC0 SC1 These bits select the counter that the control byte is destin...

Page 22: ... to read a counter on the fly without disturbing the counting process You can only rely on directly read counter data if the counting process is suspended by bringing the gate low For each counter you must specify in advance the type of read or write operation that you intend to perform You have a choice of loading reading a the high byte of the count or b the low byte of the count or c the low by...

Page 23: ... latched data 3rd Read High byte of latched data After any latching operation on a counter the contents of its hold register must be read before any subsequent latches of that counter will have any effect If a status latch command is issued before the hold register is read then the first read will read the status not the latched value 8254 Driver A simple driver is provided to perform basic counte...

Page 24: ...Initialize 1 initialize the counter Start 2 begin counting Sincestart 4 return the number of events since the start Sincelast 8 return the number of events since last check Stop 16 stop counting events Reset 32 reset number of events to 0 unsigned event_counter unsigned BaseAddress int feature Generate Frequency The Generate Frequency function will generate a square wave 0 to 5V with the desired f...

Page 25: ...bit resolution a corresponding decimal number N between 0 and 4095 is calculated 2 12 4096 N 4096 V out V full scale Next the data are written to the selected analog output channel See the preceding I O Address Map In this example we will assume analog output on channel zero AO 0 outport BASE 0 N For simplicity it was assumed that the simultaneous update capability was not used Examples of this ro...

Page 26: ...ion above for each channel at each possible range 0 6 These constants are used during normal operation to calibrate the output data in real time Refer to the samples provided on disk for an example of using this data In addition to a and b as shown above the EEPROM contains a table of ranges assigned to each channel Starting at Base F0 16 base addresses contain one byte each from 0 6 indicating th...

Page 27: ... program provided is generally the easiest method of ensuring the table remains accurate Word Address Channel Value Range Base F0h Channel 0 0 0 5 V Base F1h Channel 1 Base F2h Channel 2 1 0 2 5 V Base F3h Channel 3 Base F4h Channel 4 2 0 10 V Base F5h Channel 5 Base F6h Channel 6 3 5 5 V Base F7h Channel 7 Base F8h Channel 8 4 2 5 2 5V Base F9h Channel 9 Base FAh Channel 10 5 10 V 10 V Base FBh C...

Page 28: ... 7 Out Analog DAC 7 Output 27 Return GND Return Analog Ground 9 D A 8 Out Analog DAC 8 Output 28 Return GND Return Analog Ground 10 D A 9 Out Analog DAC 9 Output 29 Return GND Return Analog Ground 11 D A 10 Out Analog DAC 10 Output 30 Return GND Return Analog Ground 12 D A 11 Out Analog DAC 11 Output 31 Return GND Return Analog Ground 13 D A 12 Out Analog DAC 12 Output 32 Return GND Return Analog ...

Page 29: ...igital I O Port A Bit 5 26 Return Ground 7 Digital I O Port A Bit 6 27 Digital I O Port C Bit 4 8 Digital I O Port A Bit 7 28 Digital I O Port C Bit 5 9 Return Ground 29 Digital I O Port C Bit 6 10 Return Ground 30 Digital I O Port C Bit 7 11 Digital I O Port B Bit 0 31 Return Ground 12 Digital I O Port B Bit 1 32 Return Ground 13 Digital I O Port B Bit 2 33 Clock In 14 Digital I O Port B Bit 3 34...

Page 30: ...6 Digital I O Port B Bit 3 8 Digital I O Port B Bit 4 27 Digital I O Port B Bit 5 9 Digital I O Port B Bit 6 28 Digital I O Port B Bit 7 10 Return Ground 29 Return Ground 11 Digital I O Port C Bit 0 30 Digital I O Port C Bit 1 12 Digital I O Port C Bit 2 31 Digital I O Port C Bit 3 13 Return Ground 32 Return Ground 14 Digital I O Port C Bit 4 33 Digital I O Port C Bit 5 15 Digital I O Port C Bit 6...

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