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ACCES I/O Products, Inc. 

MADE IN THE USA 

PCIe-ADIO16-16F Family Manual 

 

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Rev B3d 

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HAPTER 

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OFTWARE 

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NTERFACE

 

How to use 

The ADAS3022 is a flexible data acquisition system-on-chip that has numerous features and modes of operation, and additional modes and features are added by our advanced FPGA 
design. 
This flexibility can seem overwhelming, but we’ve designed our AIOAIO.dll API to make using this ADC simple for 99% of customer use-cases, based on 30+ years of customer feedback. 
We strongly recommend you ignore the register details provided in Chapter 7: Software Interface and the discussions regarding low-level control of the ADC in the second half of this 
chapter.  Instead, simply refer to the AIOAIO Software Reference (.html) manual [link] and the source code to the variety of sample programs provided in the Software Installation 
Package [link]. 
Tip: Taking data from every channel can be as simple as calling “ADC_GetImmediateScanV(0, rangeCode, &data);”, which converts all channels at the specified range and stuffs the data 

(as double-precision floating point Voltages) into the data array.  This function can be called many thousands of times per second.  Please refer to the samples and the software reference 
for details on this and other available API functions, including how to acquire 1MHz data via callback or polling. 

Advanced Topics 

BASIC, ADVANCED, AND NON-SEQUENCED MODES 

The ADAS3022 uses the SEQ1:0 bits in the +38 and +3C control registers to select between non-sequenced mode, basic sequence mode, and advanced sequence mode. 

SEQ1  SEQ0  Mode 

Description 

non-Sequenced   The ADAS will acquire data from the channel specified in the INx2:0 bits, at the gain specified in the Gain2:0 bits. 

Modify Basic 
Sequence 

Allows the gain and such to be modified while running a basic sequence, without starting conversions over at CH0. 

Advanced 

Sequence  

Acquires Channel 0 using the gain selected via +18 bits 2:0.  Conversion-starts will automatically cycle through the channels from CH0 through INx2:0, 

and each channel is acquired at the per-channel gain set in +18.  The sequence repeats, starting at CH0 after INx2:0 is acquired. 

Basic Sequence  

Acquires channel 0 using the gain set in Gain2:0.  Conversion-starts will automatically cycle through the channels from CH0 through INx2:0, but all 
channels are acquired using the gain set in Gain2:0 rather than using the gains from +18. The sequence repeats, starting at CH0 after INx2:0 is 
acquired. 

SOFTWARE, PERIODIC, AND EXTERNAL START ADC CONVERSION TIMING MODES 

ADC data can be acquired periodically, synchronous to an external digital input, or asynchronously via software command. 
Single, Asynchronous: If the +10 ADC Timing divisor is zero then writing to +38 or +3C with bit 16 set (to 1) will initiate a single ADC Start Event under software control. 
Periodic, Asynchronous: If the +10 ADC Timing divisor is non-zero, and the External ADC Trigger Digital Input Secondary function is 

not

 enabled, writing to +38 with bit 16 set will initiate a 

single ADC Start Event, and subsequent events will occur at the rate selected via +10’s divisor.  This is “software initiated periodic timed ADC” data.  Note: con3C before this write 
to +38. 
External Trigger, Periodic, Synchronous: If the +10 ADC Timing divisor is non-zero, and the External ADC Trigger Digital Input Secondary function 

is

 enabled, writing to +38 with bit 16 set 

ARMS

 the card to begin the periodic collection of ADC data.  No data will be collected until the selected edge occurs on the ADC Trigger input. (Refer to +44 for additional details on the 

Digital I/O Secondary Functions.)  Once triggered, data will be collected until manually stopped by w38 with bit 16 clear (or various resets, etc.). 
External Start, Single, Synchronous: The digital input secondary function “ADC Start” can be configured to initiate individual ADC Start Events on a selected edge input. 

Summary of Contents for PCIe-ADI12-16

Page 1: ...Sio com 10623 Roselle Street 800 326 1649 http accesio com PCIe ADIO16 16F San Diego CA 92121 1506 USA sales accesio com MADE IN THE USA 16 ANALOG INPUT 4 ANALOG OUTPUT 16 DIGITAL I O FOR PCI EXPRESS...

Page 2: ...A D Scan Start mode optimizes inter channel timing High impedance 8 channel input 1 M 32k FIFO plus DMA for efficient robust data streaming 16 Digital I O pins with flexible secondary functions Four 1...

Page 3: ...0 Ch 0 1 35 ADC IN 1 Ch 0 ADAS3022 1 ADC IN 2 Ch 1 3 37 ADC IN 3 Ch 1 ADC IN 4 Ch 2 5 39 ADC IN 5 Ch 2 ADC IN 6 Ch 3 7 41 ADC IN 7 Ch 3 ADC IN 8 Ch 4 9 43 ADC IN 9 Ch 4 ADC IN 10 Ch 5 11 45 ADC IN 11...

Page 4: ...CH0 1 0 Advanced Sequence Acquires Channel 0 using the gain selected via 18 bits 2 0 Conversion starts will automatically cycle through the channels from CH0 through INx2 0 and each channel is acquir...

Page 5: ...ol bit and status 4 W DAC Control DAC LTC2664 Command Register bits 8 W DAC Waveform Divisor DAC Waveform Points second divisor Base Clock DAC Waveform Rate this register C R ADC Base Clock Frequency...

Page 6: ...to their power on reset state see each ADC Register for more details RST BOARD Writing a 1 will reset the entire device to its power on reset state All RST bits are command bits a 1 causes the reset t...

Page 7: ...llion 125MHz but for broadest compatibility software should always read this register during init and always use the read value when calculating what if any divisor to write to the ADC Rate Divisor re...

Page 8: ...19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RSV AIN 15 GAIN2 0 RSV AIN 14 GAIN2 0 RSV AIN 13 GAIN2 0 RSV AIN 12 GAIN2 0 RSV AIN 11 GAIN2 0 RSV AIN 10 GAIN2 0 RSV AIN 9 GA...

Page 9: ...rol 38 for important information about the Channel bits re Differential operation Diff SET indicates the paired ADC Counts were sampled in Differential mode Refer to ADC Control 38 for important infor...

Page 10: ...5 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name WDG UNUSED EXT1 EXT0 LDAC FOF FAF DTO DDONE ADCSTART ADCTRIG UNUSED enEXT1 enEXT0 enLDAC enFOF enFAF enDTO enDDONE enADCSTART enADCTRIG Read IRQ Status to determin...

Page 11: ...as a configurable active edge rising or falling SET the corresponding edgeXXX bit to select rising edge CLEAR the bit for falling edge IOGx SET each IOGx bit to configure the digital I O bits in the a...

Page 12: ...ave introduced a new source of latency the kernel userland division Application code runs in userland which must transition to the kernel in order to perform any hardware operation This transition add...

Page 13: ...all applicable EM interference and emission standards However as they are intended for use installed on motherboards and inside the chassis of industrial PCs important care in the selection of PC and...

Page 14: ...and invoiced COVERAGE FIRST THREE YEARS Returned unit part will be repaired and or replaced at ACCES option with no charge for labor or parts not excluded by warranty Warranty commences with equipmen...

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