ACE-3105, ACE-3205 Ver. 5.2
Overview
D-1
Appendix
D
Clock Modes
This appendix explains the different clock modes (system timing) supported by
ACE-3105, ACE-3205.
D.1
Overview
The ACE-3105, ACE-3205 internal clock mechanism supports the synchronization
(frequency lock) of all ports to a single clock source, which serves as the unit's
system clock.
The system clock is referenced from the incoming (RX) traffic of a specific port or
an IMA group, which was chosen to serve as benchmark for all other ports. In
addition, if a dedicated clock recovery hardware component is installed in the unit
(as ordered), the system clock can be derived (per configuration) from an
incoming pseudowire connection (see
Section
,
).
Accordingly, the synchronization of all ports to a single clock source is achieved
by:
•
Configuring the transmit (TX) clock of each specific port to System mode (see
,
)
•
Configuring the system's master and fallback clocks (see
Section
,
).
Clock States
Three clock states are possible (see also
):
•
State A – The master (primary) clock is the active system clock
•
State B – The fallback (secondary) clock is the active system clock
•
State C – Both the master and fallback clocks are inactive. In this case, the
internal oscillator serves as active clock.
Clock Availability
The master and fallback clocks can be either:
•
Available – the relevant port's clock (master or fallback)
can serve the active
reference clock, for example when the line is OK and the port is enabled; or
•
Not Available – the relevant port's clock (master or fallback)
cannot serve as
the reference clock, due to port disabling, failure in the receive (RX) line, or
lack of configuration for the fallback clock.
