Appendix
D Clock Modes
Installation and Operation Manual
D-2
Overview
ACE-3105, ACE-3205 Ver. 5.2
Accordingly, the ACE-3105, ACE-3205 clock mechanism assigns an available clock
(master or fallback) as the system clock. In the non-reversible mode, however,
the fallback clock continues to be the system clock even if the master clock
becomes available.
Triggers for Clock State Transitions
There are several triggers that may cause a clock state transition:
•
The master/fallback receive (RX) line has failed
•
The master/fallback receive (RX) line has been restored
•
The master/fallback clock's port has been disabled
•
The master/fallback clock's port has been enabled
•
The master/fallback clock configuration has changed.
The following figure illustrates the clock state transitions:
Figure
D-1. Clock State Transitions
