2-68
Service Guide
Table 2-8
65555 Pin Functions
Ball
Pin Name
Type
Active
Description
U2
T3
R4
T2
U1
R3
T1
R2
R1
P2
N3
P1
N2
M4
M3
N1
J1
J2
H1
J3
J4
H2
G1
H3
G3
F2
E1
F3
D1
E2
F4
E3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
PCI Address/Data Bus
Address and data are multiplexed on the same
pins. A bus transaction consists of an address
phase followed by one or more data phases (both
read and write bursts are allowed by the bus
definition).
The address phase is the clock cycle in which
FRAME# is asserted (AD0-31 contain a 32-bit
physical address) For l/O, the address is a byte
address. For memory and configuration, the
address is a DWORD address. During data
phases AD0-7 contain the LSB and 24-31 contain
the MSB. Write data is stable and valid when
IRDY# is asserted; read data is stable and valid
when TRDY# is asserted. Data transfers only
during those clocks when both IRDY# and
TRDY# are asserted.
C/BE3-0 Command Type Support
0000
Interrupt Acknowledge
0001
Special Cycle
0010
I/O Read
Y
0011
I/O Write
Y
0100
-reserved-
0101
-reserved-
0110
Memory Read
Y
0111
Memory Write
Y
1000
-reserved
1001
-reserved-
1010
Configuration Read
Y
1011
Configuration Write
Y
1100
Memory read Multiple
1101
Dual Address Cycle
1110
Memory Read Line
1111
Memory Read & Invalidate
P3
M2
K3
F1
C/BE0#
C/BE1#
C/BE2#
C/BE3#
In
In
In
in
Low
Low
Low
Low
Bus Command/Byte Enables. During the address
phase of a bus transaction, these pins define the
bus command (see list above). During the data
phase, these pins are byte enables that
determine which byte lanes carry meaningful
data: byte 0 corresponds to AD07, byte 1 to 8-15,
byte 2 to 16-23. and byte 3 to 2431
G2
IDSEL
In
High
Initialization Device Select. Used as a chip select
during configuration read and write transactions
Note:
All signals listed above are powered by BVCC and GND.
Summary of Contents for 390 Series
Page 15: ...System Introduction 1 3 Figure 1 2 PCB No 96183 1A Mainboard Layout Bottom ...
Page 96: ...2 50 Service Guide 2 3 3 Pin Configuration Figure 2 4 FDC37C67 TQFP Pin Diagram ...
Page 97: ...Major Chips Description 2 51 Figure 2 5 FDC37C67 QFP Pin Diagram ...
Page 102: ...2 56 Service Guide 2 3 6 Block Diagram Figure 2 6 FDC37C67 Block Diagram ...
Page 126: ...2 80 Service Guide 2 5 4 1 Functional Block Diagram Figure 2 10 M38813 Block Diagram ...
Page 128: ...2 82 Service Guide 2 6 2 Pin Diagram Figure 2 11 YMF715 Block Diagram ...
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