Major Chips Description
2-73
Notes for table below
:
•
To accommodate a wide variety of panel types, the graphics controller has been designed to output its
data in any of a number of formats. These formats include different data widths for the colors belonging
to each pixel, and the ability to accommodate different pixel data transfer timing requirements.
•
For STN-DD panels, pins PO through P35 are organized into groups corresponding to the upper and
lower parts of the panel. The names of the signals for the upper and lower parts follow a naming
convention of Uxx and Lxx, respectively.
•
For panels that require a pair of adjacent pixels be sent with every shift clock, pins PO through P35 are
organized into groups corresponding to the first and second (from right to left) pixels of each pair of pixels
being sent. The names of the signals for the first and second pixels of each such pair follow a naming
convention of Fxx and Sxx, respectively.
•
Panels that transfer data on both edges of SHFCLK are also supported. See the description for register
FR12 for more details.
Mono
Mono
Mono
Color
Color
Color
Color
Color
Color
Color
Color
Color
SS
DD
DD
TFT
TFT
TFT
TFT HR
STN SS
STN SS
STN DD
STN DD
STN DD
Pin#
Pin
Name
8-bit
8=bit
16 bit
9/12/16bit
18/24 bit
36 bit
18/24 bit
8-it(4bP)
8-bit(4bp)
8-bit(4bp)
8-bit(4bp)
8-bit
W6
P0
P0
UD3
UD7
B0
B0
FB0
FB0
R1
R1
UR1
UR0
UR0
V7
P1
P1
UD2
UD6
B1
B1
FB1
B1
B1
G1
UG1
UG0
UG0
Y6
P2
P2
UD1
UD5
B2
B2
FB2
FB2
G2
B1
UB1
UB0
UB0
W7
P3
P3
UD0
UD4
B3
B3
FB3
FB3
R3
R2
UR2
UR1
LR0
V8
P4
P4
LD3
UD3
B4
B4
FB4
SB0
B3
G2
LR1
LR0
LG0
Y7
P5
P5
LD2
UD2
G0
B5
FB5
SB1
G4
B2
LG1
LG0
LB0
W8
P6
P6
LD1
UD1
G1
B6
SB0
SB2
R5
R3
LB1
LB0
UR1
U9
P7
P7
LD0
LD0
G2
B7
SB1
SB3
B5
G3
LR2
LR1
UG1
V9
P8
-
-
LD7
G3
G0
SB2
FG0
-
B3
-
UG1
UB1
Y8
P9
-
-
LD6
G4
G1
SB3
FG1
-
R4
-
UB1
LR1
W9
P10
-
-
LD5
G5
G2
SB4
FG2
-
G4
-
UR2
LG1
Y9
P11
-
-
LD4
R0
G3
SB5
FG3
-
B4
-
UG2
LB1
V10
P12
-
-
LD3
R1
G4
FG0
SG0
-
R5
-
LG1
UR2
W10
P13
-
-
LD2
R2
G5
FG1
SG1
-
G5
-
LB1
UG2
Y10
P14
-
-
LD1
R3
G6
FG2
SG2
-
B5
-
LR2
UB2
U10
P15
-
-
LD0
R4
G7
FG3
SG3
-
R6
-
LG2
LR2
U11
P16
-
-
-
-
R0
FG4
FR0
-
-
-
-
LG2
Y11
P17
-
-
-
-
R1
FG5
FR1
-
-
-
-
LB2
W11
P18
-
-
-
R2
SG0
FR2
-
-
-
-
UR3
V11
P19
-
-
-
-
R3
SG1
FR3
-
-
-
-
UG3
Y12
P20
-
-
-
-
R4
SG2
SR0
-
-
-
UB3
Y13
P21
-
-
-
-
R5
SG3
SR1
-
-
-
-
LR3
V12
P22
-
-
-
-
R6
SG4
SR2
-
-
-
-
LG3
U12
P23
-
-
-
-
R7
SG5
SR3
-
-
-
-
LB3
W13
P24
-
-
-
-
-
FR0
-
-
-
-
-
-
Y14
P25
-
-
-
-
-
FR1
-
-
-
-
-
-
V13
P26
-
-
-
-
-
FR2
-
-
-
-
-
-
W14
P27
-
-
-
-
-
FR3
-
-
-
-
-
-
Y15
P28
-
-
-
-
-
FR4
-
-
-
-
-
-
V14
P29
-
-
-
-
-
FR5
-
-
-
-
-
-
W15
P30
-
-
-
-
-
SR0
-
-
-
-
-
-
Y16
P31
-
-
-
-
-
SR1
-
-
-
-
-
-
V15
P32
-
-
-
-
-
SR2
-
-
-
-
-
-
Y17
P33
-
-
-
-
-
SR3
-
-
-
-
-
-
W16
P34
-
-
-
-
-
SR4
-
-
-
-
-
-
U15
P35
-
-
-
-
-
SR5
-
-
-
-
-
-
Y15
SHFCLK
SHFCLK
SHFCLK
SHFCLK
SHFCLK
SHFCLK
SHFCLK
SHFCLK
SHFCLK
SHFCLK
SHFCLK
SHFCLK
SHFCLK
Pixels/Clock:
8
8
16
1
1
2
2
2-2/3
5-1/3
2-2/3
5-1/3
8
Summary of Contents for 390 Series
Page 15: ...System Introduction 1 3 Figure 1 2 PCB No 96183 1A Mainboard Layout Bottom ...
Page 96: ...2 50 Service Guide 2 3 3 Pin Configuration Figure 2 4 FDC37C67 TQFP Pin Diagram ...
Page 97: ...Major Chips Description 2 51 Figure 2 5 FDC37C67 QFP Pin Diagram ...
Page 102: ...2 56 Service Guide 2 3 6 Block Diagram Figure 2 6 FDC37C67 Block Diagram ...
Page 126: ...2 80 Service Guide 2 5 4 1 Functional Block Diagram Figure 2 10 M38813 Block Diagram ...
Page 128: ...2 82 Service Guide 2 6 2 Pin Diagram Figure 2 11 YMF715 Block Diagram ...
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