2-74
Service Guide
Table 2-8
65555 Pin Functions (continued)
Ball
Pin Name
Type
Active
Description
CRT Interface
U3
HYSNC(CSYNC)
Out
Both
CRT Horizontal Sync (polarity is programmable) or
"Composite Sync" for support of various external
NTSC/PAL encoder chips
V2
VSYNC
Out
Both
CRT Vertical Sync (polarity is programmable)
Y3
V4
W3
RED
GREEN
BLUE
Out
Out
Out
Analog
Analog
Analog
CRT analog video outputs from the internal color
palette DAC. The DAC is designed for a 37.5S2
equivalent load on each pin (e.g. 75Q resistor on
the board, in parallel with the 75D CRT load)
W2
RSET
In
N/A
Set point resistor for the internal color palette DAC.
A 560 Q 1% resistor is required between RSET and
AGND
V3
U4
DDC
DATA(GPIO2)
DDC CLK(GPIO3)
I/O
I/O
High
High
General purpose I/0, suitable for use as DDC data.
General purpose I/0, suitable for use as DDC
DATA. These two pins are functionally suitable for a
DDC interface between the 65555 and a CRT
monitor
Note:
HSYNC, VSYNC, GPIO2, and gpio3 are powered by CVCC and GND. RED, GREEN, BLUE and
RSET are powered by AVCC and AGND.
Power/Ground and Standby Control
U5
AVCC
VCC
-
Analog power and ground pins for noise isolation
for the internal color palette DAC. AVCC should be
isolated from digital VCC as described in the
Functional Description of the internal color palette
DAC. For proper DAC operation, AVCC should not
be greater than IVCC. AGND should be common
with digital ground but must be lightly decoupled to
AVCC. See the Functional Description of the
internal color palette DAC for further information
B3
A2
C4,D5
A3, B4
W1
SVCC
SGND
PVCC
PGND
CVCC
VCC
GND
VCC
GND
VCC
-
-
-
Analog power and ground pins for noise isolation
for the internal clock synthesizer (for MCLK). Must
be the same as IVCC, 3.3V.
Analog power and ground pins for noise isolation
for internal clock synthesizer (for VCLK). Must be
the same as IVCC.
SVCC/SGND and PVCC/PGND pairs must be
carefully decoupled individually. Refer also lo the
section on clock ground layout in the Functional
Description.
Power for CRT Interface, 3.3V.
D9, &
W12
D14
D7
G17
G4,
P17
IVCC
GND
VCC
GND
-
-
Power/Ground (Internal Logic), 3.3V. Note that this
voltage must be the same as SVCC and PVCC
(voltages for internal clock synthesizers)
Summary of Contents for 390 Series
Page 15: ...System Introduction 1 3 Figure 1 2 PCB No 96183 1A Mainboard Layout Bottom ...
Page 96: ...2 50 Service Guide 2 3 3 Pin Configuration Figure 2 4 FDC37C67 TQFP Pin Diagram ...
Page 97: ...Major Chips Description 2 51 Figure 2 5 FDC37C67 QFP Pin Diagram ...
Page 102: ...2 56 Service Guide 2 3 6 Block Diagram Figure 2 6 FDC37C67 Block Diagram ...
Page 126: ...2 80 Service Guide 2 5 4 1 Functional Block Diagram Figure 2 10 M38813 Block Diagram ...
Page 128: ...2 82 Service Guide 2 6 2 Pin Diagram Figure 2 11 YMF715 Block Diagram ...
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