Major Chips Description
2-11
Table 2-2
PCI1250 Terminal Functions
Name
No.
I/O Type
Function
IOWR
M02
C19
O
I/O Write IOWR is driven low by the PCI1250A to
strobe write data into 16-bit l/O PC Cards during
host l/O write cycles.
DMA Read. This pin is used as the DMA write
strobe during DMA operations from a 16-bit PC
Card that supports DMA. The PCI1250A asserts
this signal during transfers from host memory to
the PC Card.
OE
L03
C20
O
Output Enable. OE is driven low by the PCl1250A
to enable 16-bit Memory PC Card data output
during host memory read cycles.
DMA terminal count. This pin is used as TC during
DMA operations to a 16-bit PC Card which supports
DMA. The PCI1250A asserts this signal to indicate
terminal count for a DMA write operation
READY/IREQ
Y04
A10
I
The ready function is provided by the READY signal
when the 16-bit PC Card and the host socket are
configured for the memory-only interface. READY
is driven low by the 16-bit Memory PC Cards to
indicate that the memory card circuits are busy
processing a previous write command. READY is
driven high when the 16-bit Memory PC Card is
ready to accept a new data transfer command.
Interrupt Request. IREQ is asserted by a 16-bit l/O
PC Card to indicate to the host that a device on the
16-bit l/O PC Card requires service by the host
software. IREQ is high (deasserted) when no
interrupt is requested.
REG
Y02
B12
O
Attribute memory select. REG remains high for all
common memory accesses. When REG is asserted
access is limited to attribute memory (OE or WE
active) and to 1he l/O space (IORD or IOWR
active}. Attribute memory is a separately accessed
section of card memory and is generally use to
record card capacity and other configuration and
attribute information.
DMA acknowledge. This pin is used as a DACK
during DMA operations to a 16-bit PC Card that
supports DMA. The PCI1250A asserts this signal to
indicate a DMA operation. This signal is used in
conjunction with the DMA read (IOWR) or DMA
write (IORD) strobes to transfer data.
RESET
W01
C13
O
PC Card reset. RESET forces a hard reset to a 16-
bit PC Card
WAIT
V05
B10
I
Bus cycle wait. WAIT is driven by a 16-bit PC Card
to delay the completion of (i.e.. extend) the memory
or l/O cycle that is in progress.
Summary of Contents for 390 Series
Page 15: ...System Introduction 1 3 Figure 1 2 PCB No 96183 1A Mainboard Layout Bottom ...
Page 96: ...2 50 Service Guide 2 3 3 Pin Configuration Figure 2 4 FDC37C67 TQFP Pin Diagram ...
Page 97: ...Major Chips Description 2 51 Figure 2 5 FDC37C67 QFP Pin Diagram ...
Page 102: ...2 56 Service Guide 2 3 6 Block Diagram Figure 2 6 FDC37C67 Block Diagram ...
Page 126: ...2 80 Service Guide 2 5 4 1 Functional Block Diagram Figure 2 10 M38813 Block Diagram ...
Page 128: ...2 82 Service Guide 2 6 2 Pin Diagram Figure 2 11 YMF715 Block Diagram ...
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