Major Chips Description
2-25
Table 2-3
M1531 Signal Descriptions
Signal
Type
Description
KENJ/INV
O
Group A
Cache Enable Output. This signal is connected to the CPU's KENJ and INV
pins. KENJ is used to notify the CPU whether the address of the current
transaction is cacheable. INV is used during L1 snoop cycles. The M1531
drives this signal high (low) during the EADSJ assertion of a PCI master write
(read) snoop cycle.
SMIACTJ
I
Group A
SMM Interrupt Active. This signal is asserted by the CPU to inform the M1531
that SMM mode is being entered.
HD[63:0]
I/O
Group A
Host Data Bus Lines. These signals are connected to the CPU's data bus.
HD[63] applies to the most significant bit and HD[0] applies to the least
significant bit.
MPD[7:0]
I/O
Group C
DRAM Parity /ECC check bits. These are the 8 bits for parities/ECC check
bits over DRAM data bus. MPD[7] applies to the most significant bit and
MPD[0] applies to the least significant bit.
RASJ[7] /
SRASJ[0]
O
Group C
Row Address Strobe 7, (FPM/EDO) of DRAM row 7.
SDRAM Row Address Strobe (SDRAM) copy 0. It connects to SDRAM RASJ.
This is a multifunction pin and determined by Index-5Ch bit0.
RASJ[6] /
SCASJ[0]
O
Group C
Row Address Strobe 6, (FPM/EDO) of DRAM row 6.
SDRAM Column address strobe (SDRAM) copy 0. It connects to SDRAM
CASJ. This is a multifunction pin and determined by Index-5Ch bit0.
RASJ[5:0]
O
Group C
Row Address Strobes. These signals are used to drive the corresponding
RASJs of FPM/EDO DRAMs. In SDRAM, they are used to drive the
corresponding SDRAM CSJs.
CASJ[7:0] /
DQM[7:0]
O
Group C
Column Address Strobes or Synchronous DRAM Input/Output Data Mask.
These CAS signals should be connected to the corresponding CASJs of each
bank of DRAM. The value of CASJs equals that of HBEJs for write cycles.
During DRAM read cycles, all of CASJs will be active. In SDRAM, these pins
act as synchronized output enables during a read cycle and the byte mask
during write cycle, these pins are connected to SDRAM DQM[7:0].
MA[11:2]
O
Group C
DRAM Address Lines. These signals are the address lines[11:2] of all
DRAMs. The M1531 supports DRAM types ranging from 256K to 64Mbits.
MAA[1:0]
O
Group C
Memory Address copy A for [1:0]. These signals are the address lines[1:0]
copy 0 of all DRAMs.
MAB[1:0]
O
Group C
Memory Address copy B for [1:0]. These signals are the address lines[1:0]
copy 1 of all DRAMs.
MWEJ[0]
O
Group C
DRAM Write Enable. This is the DRAM write enable pin and behaves
according to the early-write mechanism, i.e. , it activates before the CASJs do.
For refresh cycles, it will remain deasserted.
MD[63:0]
I/O
Group C
Memory Data. These pins are connected to DRAM’s data bits. MD[63]
applies to the most significant bit and MD[0] applies to the least significant bit.
CLKEN[0]/
REQJ[4]
I/O
Group C
SDRAM Clock Enable Copy 0 or PCI Master Request. This signal is used as
SDRAM clock enable copy 0 to do self refresh during suspend. It can also be
used as bus request signal of the fifth PCI master. This function is controlled
by Index -5Dh bit 1.
Summary of Contents for 390 Series
Page 15: ...System Introduction 1 3 Figure 1 2 PCB No 96183 1A Mainboard Layout Bottom ...
Page 96: ...2 50 Service Guide 2 3 3 Pin Configuration Figure 2 4 FDC37C67 TQFP Pin Diagram ...
Page 97: ...Major Chips Description 2 51 Figure 2 5 FDC37C67 QFP Pin Diagram ...
Page 102: ...2 56 Service Guide 2 3 6 Block Diagram Figure 2 6 FDC37C67 Block Diagram ...
Page 126: ...2 80 Service Guide 2 5 4 1 Functional Block Diagram Figure 2 10 M38813 Block Diagram ...
Page 128: ...2 82 Service Guide 2 6 2 Pin Diagram Figure 2 11 YMF715 Block Diagram ...
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