2-36
Service Guide
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Independent programmable level/edge triggered channels
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Counter/Timers
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8254 compatible timers for System Timer, Refresh Request, Speaker Output Use
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Distributed DMA supported
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7 DMA Channels can be arbitrarily programmed as distributed channel
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Serialized IRQ supported
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Quiet/Continuous mode
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Programmable (default 21) IRQ/DATA frames
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Programmable START frame pulse width
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Plug-and-Play port supported
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One programmable chip select
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Two steerable interrupt request lines
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Built-in keyboard controller
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Built-in PS/2/AT keyboard and PS/2 mouse controller
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Supports up to 256-KB ROM size decoding
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Supports positive/subtractive decode for ISA device
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PMU features
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Full-support for ACPI and OS directed power management
•
CPU SMM Legacy mode and SMI feature supported
•
Supports programmable STPCLKJ: throttle/CKONSTP/CKOFFSTP control
•
Supports I/O trap for I/O restart feature
•
PMU operation states :
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On
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Standby
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Sleeping ( Power-On Suspend )
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Suspend ( Suspend to DRAM)
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Suspend to HDD
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Soft Off
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Mechanical Off
•
APM state detection and control logic supported
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Global and local device power control logic
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Ten Programmable Timers: Standby / LB / LLB / APMA / APMB / Global_Display /
Primary_IDE / Secondary_IDE / SIO&Audio / Programmable IO Region
•
Provides system activity and display activity monitorings, including:
−
Video
−
Audio
Summary of Contents for 390 Series
Page 15: ...System Introduction 1 3 Figure 1 2 PCB No 96183 1A Mainboard Layout Bottom ...
Page 96: ...2 50 Service Guide 2 3 3 Pin Configuration Figure 2 4 FDC37C67 TQFP Pin Diagram ...
Page 97: ...Major Chips Description 2 51 Figure 2 5 FDC37C67 QFP Pin Diagram ...
Page 102: ...2 56 Service Guide 2 3 6 Block Diagram Figure 2 6 FDC37C67 Block Diagram ...
Page 126: ...2 80 Service Guide 2 5 4 1 Functional Block Diagram Figure 2 10 M38813 Block Diagram ...
Page 128: ...2 82 Service Guide 2 6 2 Pin Diagram Figure 2 11 YMF715 Block Diagram ...
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