Major Chips Description
2-11
Table 2-2
M1521 Signal Descriptions (continued)
Signal
Pin
Type
Description
Secondary Cache Interface
CCSJ/CB4
W16
O
Synchronous SRAM chip select or Cache Address
line 4 copy. This pin has two modes of operation
depending on the type of SRAM selected via
hardware strapping options or programming the CC
register.
GWEJ
Y16
O
Synchronous SRAM Global Write Enable or
Asynchronous SRAM Write Enable.
COEJ
U15
O
Synchronous/Asynchronous SRAM Output Enable.
BWEJ/CGCSJ
Y17
O
Synchronous SRAM Byte-Write Enable/
Asynchronous SRAM Global Chip Select.
TIO[10]/
MWEJ[1]
Y20
I/O
SRAM Tag[10] or another copy of MWEJ.
TIO[9]/
SRASJ[1]
Y19
I/O
SRAM Tag[9] or synchronous DRAM (SDRAM) RAS
copy 1.
TIO[8]/
SCASJ[1]
W19
I/O
SRAM Tag[8] or synchronous DRAM (SDRAM) CAS
copy 1.
TIO[7:0]
Y18, W18, V18, T14,
V17, U17, U16, P16
I/O
SRAM Tag[7:0]. This pin contains the L2 tag
address for 256 KB L2 caches. TIO[6:0] contain the
L2 tag address and TIO7 contains the L2 cache valid
bit for 512 KB caches.
TWEJ
V16
O
Tag Write Enable. This signal, when asserted,
writes into the external tag new state and tag
addresses.
PCI Interface
AD[31:28]
AD[27:24]
AD[23:20]
AD[19:16]
AD[15:12]
AD[11:08]
AD[07:04]
AD[03:00]
A2, B2, A3, B3, A4, B4,
C4, D6, B5, C5, A6, B6,
C6, A7, B7, C7, C8, A9,
B9, C9, A10, B10, C10,
A11, C11, A12, B12,
C12, A13, B13, A14,
A15
I/O
PCI Address-and-Data Bus Lines. These lines
connect to the PCI bus. AD[31:0] contain the
information of address or data for PCI transactions.
CBEJ[3:0]
A5, A8, B8, B11
I/O
PCI Bus Command and Byte Enables. Bus
commands and byte enables are multiplexed in
these lines for address and data phases,
respectively.
FRAMEJ
E6
I/O
Cycle Frame of PCI Buses. This indicates the
beginning and duration of a PCI access.
DEVSELJ
E9
I/O
Device Select. When the target device has decoded
the address as its own cycle, it asserts DEVSELJ.
IRDYJ
E7
I/O
Initiator Ready. This indicates the initiator is ready
to complete the current data phase of transaction.
Summary of Contents for AcerNote Light 370P
Page 6: ...vi ...
Page 26: ...1 8 Service Guide Figure 1 5 Main Board Layout Bottom Side ...
Page 49: ...System Introduction 1 31 1 5 1 3 Power Management Figure 1 14 Power Management Block Diagram ...
Page 55: ...System Introduction 1 37 1 6 System Block Diagram Figure 1 15 System Block Diagram ...
Page 64: ...Major Chips Description 2 7 2 2 5 Pin Diagram Figure 2 4 M1521 Pin Diagram ...
Page 99: ...2 42 Service Guide 2 5 3 Pin Diagram Figure 2 10 C T 65550 Pin Diagram ...
Page 117: ...2 60 Service Guide Figure 2 12 Functional block diagram CardBus Card Interface ...
Page 119: ...2 62 Service Guide Figure 2 14 PCI to CardBus terminal assignments ...
Page 135: ...2 78 Service Guide 2 7 3 Pin Diagram Figure 2 16 NS87336VJG Pin Diagram ...
Page 145: ...2 88 Service Guide 2 8 2 Pin Diagram Figure 2 17 YMF715 Block Diagram ...
Page 185: ...Disassembly and Unit Replacement 4 5 Figure 4 3 Disassembly Sequence Flowchart ...
Page 209: ...B 2 Service Guide ...
Page 210: ...Exploded View Diagram B 3 ...
