Chapter 5
90
Illustration
Jumper / Header Name
Pin No. and definition
IDE Header
1: SLOT_IDERST
3: IDE_PDD7
5: IDE_PDD6
7: IDE_PDD5
9: IDE_PDD4
11: IDE_PDD3
13: IDE_PDD2
15: IDE_PDD1
17: IDE_PDD0
19: GND
21: IDE_DREQ_P
23: IDE_IOW_P*
25: IDE_IOR_P*
27: IDE_IORDY_P
29: IDE_DACK_P*
31: IDE_INTR_P
33: IDE_ADDR_P1
35: IDE_ADDR_P0
37: IDE_CS1_P*
39: P_HDLED*
2: GND
4: IDE_PDD8
6: IDE_PDD9
8: IDE_PDD10
10: IDE_PDD11
12: IDE_PDD12
14: IDE_PDD13
16: IDE_PDD14
18: IDE_PDD15
20: KEY
22: GND
24: WGATEJ
26: TK00J
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
22
24
26
28
30
32
34
36
38
40
X
SLOT_IDERST
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0
GND
IDE_DREQ_P
IDE_IOW_P*
IDE_IOR_P*
IDE_IORDY_P
IDE_DACK_P*
IDE_ADDR_P1
IDE_ADDR_P0
IDE_CS1_P*
P_HDLED*
IDE_INTR_P
GND
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
GND
GND
GND
GND
GND
CBLE_DET_P
IDE_ADDR_P2
IDE_CS3_P*
GND
Summary of Contents for AcerPower APM6
Page 2: ...II PRINTED IN TAIWAN ...
Page 14: ...Chapter 1 5 Block Diagram ...
Page 15: ...6 Chapter 1 Main Board Placement ...
Page 31: ...22 Chapter 1 Input Output Map Assignment 1 Address Device ...
Page 32: ...Chapter 1 23 Input Output Map Assignment 2 Address Device ...
Page 33: ...24 Chapter 1 Memory Map Assignment Address Device ...