2-86
Service Guide
Table 2-14
NS87336VJG Pin Descriptions (continued)
Pin
No.
I/O
Description
TC
4
I
Terminal Count. Control signal from the DMA controller to indicate
the termination of a DMA transfer. TC is accepted only when FDACK
is active. TC is active high in PC-AT and Model 30 modes, and
active low in PS/2 mode.
/TRK0
(Normal Mode)
35
I
FDC Track 0. This input indicates the controller that the head of the
selected floppy disk drive is at track zero.
/TRK0
(PPM Mode)
91
I
FDC Track 0. This pin gives an additional Track 0 signal in PPM
Mode when PNF = 0.
VDDB, C
48, 97
Power Supply. This is the 3.3V/5V supply voltage for the
PC87332VJG circuitry.
VSSB-E
40, 7,
88, 59
Ground. This is the ground for the PC87332VJG circuitry.
/WAIT
82
I
EPP Wait. This signal is used in EPP mode by the parallel port
device to extend its access cycle. It is an active low signal.
/WDATA
(Normal Mode)
37
O
FDC Write Data. This output is the write precompensated serial data
that is written to the selected floppy disk drive. Precompensation is
software selectable.
/WDATA
(PPM Mode)
81
O
FDC Write Data. This pin provides an additional Write Data signal in
PPM Mode when PNF=0. (See PE.)
/WGATE
(Normal Mode)
36
O
FDC Write Gate. This output signal enables the write circuitry of the
selected disk drive. WGATE has been designated to prevent glitches
during power-up and power-down. This prevents writing to the disk
when power is cycled.
/WGATE
(PPM Mode)
80
O
FDC Write Gate. This pin gives an additional Write Gate signal in
PPM mode when PNF = 0.
/WP
(Normal Mode)
34
I
FDC Write Protect. This input indicates that the disk in the selected
drive is write protected.
/WP
(PPM Mode)
90
I
FDC Write Protect. This pin gives an additional Write Gate signal in
PPM mode when PNF = 0.
/WR
16
I
Write. An active low input to signal a write from the microprocessor
to the controller.
/WRITE
93
O
EPP Write Strobe. This signal is used in EPP mode as write strobe.
It is active low.
X1/OSC
5
I
Crystal1/Clock. One side of an external 24 MHz/48 MHz crystal is
attached here. If a crystal is not used, a TTL or CMOS compatible
clock is connected to this pin.
X2
6
O
Crystal 2. One side of an external 24 MHz/48 MHz crystal is attached
here. This pin is left unconnected if an external clock is used.
/ZWS
1
O
Zero Wait State. This pin is the Zero Wait State open drain output
pin when bit 6 of FCR is 0. ZWS is driven low when the EPP or ECP
is written, and the access can be shortened.
Summary of Contents for Extensa 61X
Page 6: ...vi ...
Page 26: ...1 8 Service Guide Figure 1 5 Main Board Layout Bottom Side ...
Page 49: ...System Introduction 1 31 1 5 1 3 Power Management Figure 1 14 Power Management Block Diagram ...
Page 55: ...System Introduction 1 37 1 6 System Block Diagram Figure 1 15 System Block Diagram ...
Page 64: ...Major Chips Description 2 7 2 2 5 Pin Diagram Figure 2 4 M1521 Pin Diagram ...
Page 99: ...2 42 Service Guide 2 5 3 Pin Diagram Figure 2 10 C T 65550 Pin Diagram ...
Page 117: ...2 60 Service Guide Figure 2 12 Functional block diagram CardBus Card Interface ...
Page 119: ...2 62 Service Guide Figure 2 14 PCI to CardBus terminal assignments ...
Page 135: ...2 78 Service Guide 2 7 3 Pin Diagram Figure 2 16 NS87336VJG Pin Diagram ...
Page 145: ...2 88 Service Guide 2 8 2 Pin Diagram Figure 2 17 YMF715 Block Diagram ...
Page 185: ...Disassembly and Unit Replacement 4 5 Figure 4 3 Disassembly Sequence Flowchart ...
Page 209: ...B 2 Service Guide ...
Page 210: ...Exploded View Diagram B 3 ...
