SERIES AP470 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 33 -
http://www.acromag.com
- 33 -
www.acromag.com
Debounce Clock Select Register (Enhanced Mode Bank 2, Port 3, Write Only)
(BAR0 + 0x0000 0014)
This register selects the source clock for the event sense input debounce
circuitry. If bit 0 of this register is 0 (default), then the debounce source clock
is taken from I/O47 thus reducing the effective number of I/O to 47. If bit 0 is
set to 1, then the 31.25MHz internal system clock is used (recommended).
Bits 1-7 of this register are not used and will always read as zero.
WARNING: IF USING I/O47 AS THE DEBOUNCE CLOCK, DO NOT SET THE I/O
AS AN ACTIVE OUTPUT VIA THE PORT I/O REGISTERS. SETTING I/O47 AS AN
ACTIVE OUTPUT MAY CAUSE A BUS CONFLICT.
Bit(s)
FUNCTION
0
Debounce Clock Select
0
External clock on I/O47
1
Internal clock @ 31.25 MHz
7 to 1
Not Used
Bank Select (Write) & Status (Read) Register (Enhanced Mode Bank 2, Port 7, Read and Write)
(BAR0 + 0x0000 0024)
Bits 0-5 of this register are not used. Bits 6 & 7 of this register are used to
select the bank of registers to be addressed. In Enhanced Mode, three banks
(banks 0, 1, & 2) of eight registers may be addressed. Bank 0 registers are
similar to the Standard Mode bank of registers. Bank 1 allows the 48 event
inputs to be monitored and controlled. Bank 2 registers control the
debounce circuitry of the event inputs. Bits 7 and 6 select/indicate the bank
as follows:
Table 3.19 Bank Select (Write)
& Status (Read) Register
BIT 7 Bit 6
BANK OF REGISTERS
00
Bank 0 – Read/Write I/O Signals
01
Bank 1 – Event Status/Clear
10
Bank 2 – Event Debounce Control, Clock, and Duration
11
INVALID – DO NOT WRITE
Software Reset Register (Accessible in Standard and Enhanced Mode) (Read/Write)
(BAR0 + 0x0000 0044)
Writing a 1 to the bit 1 position of this register will cause a software reset to
occur. This bit is not stored and merely acts as a trigger for software reset
generation (this bit will always read back as 0). The Interrupt Enable Bit of
the Interrupt Enable and Status register is not cleared in response to a
software reset. Bits 2-7 of this register are not used and will always read
high (1’s).
