SERIES AP470 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
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http://www.acromag.com
- 42 -
www.acromag.com
4.0 THEORY OF OPERATION
This section provides a description of the basic functionality of the circuitry
used on the board. Refer to the Block Diagram shown in Figure 1, in
Appendix A, as you review this material.
4.1 Logic/Power Interface
The PCIe bus interface logic is embedded within the FPGA. This logic
includes support for PCIe commands, including: configuration read/write,
and memory read/write. In addition, the PCIe target interface uses a single
4K base address register.
A FPGA device provides the control signals required to operate the board. It
decodes the selected addresses and control signals. It also returns the
acknowledgement messages required by the carrier/CPU board per the PCIe
specification. The program for the FGPA is stored in separate Flash memory
and loaded upon power-up.
4.2 I/O Ports
The field I/O interface to the carrier board is provided through connector P2
(refer to Table 2.1). Field I/O points are NONISOLATED. This means that the
field return and logic common have a direct electrical connection to each
other. As such, care must be taken to avoid ground loops. Ignoring this effect
may cause operation errors, and with extreme abuse, possible circuit
damage.
A Field Programmable Gate Array (FPGA) is used to generate all the logic
necessary to operate the board. With respect to input acquisition, all 48
input channels support interrupts and drive the FPGA through buffers. The
input signal threshold is TTL compatible and includes hysteresis. Further,
each input port is connected such that the current status of a given output
port can be read back via the corresponding input port. Individual ports may
also be masked from writes to the port when the port is intended for input
only to help prevent contention errors.
Each port I/O line includes an integrated 4.7kΩ pull-up resistor to +5V. For
inputs, the pull-ups provide a low (false=0) input indication if the input is left
floating.
Each I/O line is in the form of an open-drain signal. Thus, any data written to
any port used as an input must be masked or always false (zero) to avoid
contention between the output circuitry and an input signal from an external
device. All 48 I/O lines are placed into the false (high output) state following
power-up or a system reset. The 4.7kΩ pull-up resistors installed on the
board provide digital high-drive capability for the output signals.
