INDUSTRIAL I/O PACK SERIES APC8640 PCI BUS CARRIER BOARD
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The PCI bus interface is implemented in the logic of the
carrier board’s PCI bus target interface chip. The PCI bus
interface chip implements PCI specification version 2.2 as an
interrupting slave including 8-bit and 16-bit data transfers to the
IP modules.
32-bit IP data transfers will be treated as two 16-bit
data transfers.
Note the APC8640 requires that system 3.3 volts is
present on the PCI bus 3.3V pins.
There are some older
systems that do not provide 3.3 Volts on the PCI bus 3.3 volt
pins. The APC8640 boards will not work in these systems.
Note that the APC8640 board is not hot-swapable
The carrier board’s PCI bus data transfer rates are shown in
Table 2.3.
Carrier Board Registers
The carrier board registers (presented in section 3) are
implemented in the logic of the carrier board’s FPGA. An outline
of the functions provided by the carrier board registers includes:
•
Identifying if memory space is enabled in the
Carrier
Identification Bits
.
•
Selecting either an 8MHz or 32MHz clock for each IP
module in the
Clock Control Register
.
•
Monitoring the error signal received from each IP module is
possible via the
IP Error Bit
.
•
Enabling of PCI bus interrupt requests from each IP module
is possible via the
IP Module Interrupt Enable Bit
.
•
Enabling of interrupt generation upon an IP module access
time out is implemented via the
Time Out Interrupt Enable
Bit.
•
Monitoring an IP module access time out is possible via the
IP Module Access Time Out Status Bit.
•
Identify pending interrupts via the carrier’s
IP Module
Interrupt Pending
Bit
.
•
Lastly, pending interrupts can be individually monitored via
the
IP Module Interrupt Pending register
.
IP Logic Interface
The IP logic interface is also implemented in the logic of the
carrier board’s FPGA. The carrier board implements ANSI/VITA
4 1995 Industrial I/O Pack logic interface specification and
includes five IP logic interfaces. The PCI bus address and data
lines are linked to the address and data of the IP logic interface.
This link is implemented and controlled by the carrier board’s
FPGA.
The PCI bus to IP logic interface link allows a PCI bus master
to:
•
Access up to 64 ID Space bytes for IP module identification
via 8-bit or 16-bit data transfers using PCI bus.
•
Access up to 128 I/O Space bytes of IP data via 8-bit or 16-
bit data transfers.
•
Access up to 8M byes of Memory Space data via 8-bit or 16-
bit data transfers.
•
Access IP module interrupt space via 8-bit or 16-bit PCI bus
data transfers.
•
Respond to two IP module interrupt requests per IP module.
As per the ANSI/VITA 4 1995 Industrial I/O Pack logic interface
specification only 4 IP modules may be running at 32MHz on the
APC8640 to comply with bus loading requirements.
When an IP module places data on the bus, for all data read
cycles, any undriven data lines are read by the PCI bus as high
because of pull-up resisters on the carrier board’s data bus.
Carrier Board Clock Circuitry
A 32MHz clock, obtained from a multiplied 8MHz clock, is
used to control the FPGA and the local bus. Clocks are then
driven to each IP module via a high speed transceiver to allow for
a module independent selectable clock. All clock lines include
series damping resistors to reduce clock overshoot and
undershoot.
PCI Interrupter
Interrupts are initiated from an interrupting IP module.
However, the carrier board will only pass an interrupt generated
by an IP module to the PCI bus if the carrier board has been first
enabled for interrupts. Each IP module can initiate two interrupts
which can be individually monitored on the carrier board. After
interrupts are enabled on the carrier board via the Interrupt
Enable Bits (see section 3 for programming details), an IP
generated interrupt is recognized by the carrier board and is
recorded in the carrier board’s Interrupt Pending Register.
A carrier board pending interrupt will cause the board to pass
the interrupt to the PCI bus provided the Interrupt Enable bits of
the carrier’s Status Register have been enabled (see section 3 for
programming details). The PC interrupt request line assigned by
the system configuration software will then be asserted. The
PC/AT will respond to the asserted interrupt line by executing the
interrupt service routine corresponding to the interrupt line
asserted. The interrupt service routine is executed only if the IRQ
on the PC/AT’s 8259 interrupt controller has been previously
unmasked (see section 3 for programming details).
The interrupt service routine should respond to an interrupt by
accessing IP Interrupt Select (INTSEL*) space. The interrupt
service routine should also conclude the interrupt routine by
writing the “End-Of-Interrupt” command to the PC/AT’s 8259
interrupt controller (see section 3 for more details).
Power Failure Monitor
The carrier board contains a 5 volts undervoltage monitoring
circuit which provides a reset to the IP modules when the 5 volt
power drops below 4.38 volts typical / 4.31 volts minimum. This
circuitry is implemented per the Industrial I/O Pack specification.
Power-On Reset
The carrier board will provide an asynchronous reset signal to
all IP modules for at least 200ms following power-up. The IP
reset signal will remain active until the FPGA is initialized.
