INDUSTRIAL I/O PACK SERIES APC8640 PCI BUS CARRIER BOARD
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BIT FUNCTION
15-12 Carried
Identification:
These bits are used for carrier identification.
Writing to these bits will result in the data being
stored. Reading these bits will result in the inverse
of the stored value. Reset Condition: “1010” if
Memory Space is not supported. “1011” if memory
space is supported.
Memory space support is
controlled via a configuration jumper.
11-09
Not Used (bits read as logic “0”)
08
Write
Only
Software Reset
Writing a “1” to this bit causes a software reset.
Writing a “0” or reading this bit has no effect.
When set, the software reset pulse will have a
duration of 1
μ
s (microsecond).
07-06
Not Used (bits read as logic “0”)
05
Read
And
Write
IP Module Access Time Out Interrupt Pending
This bit will be "1" when there is a IP Module
Access Time Out interrupt pending. This bit
will be "0" when there is no interrupt pending.
Reset condition: Set to "0". Writing a “1” to
this bit will release the pending interrupt.
04
Read
Only
IP Module Access Time Out Status
Status bit to indicated that the last IP module
access has timed out. This bit only reflects the
last IP module access.
“0” if last IP module access did not time out.
“1” if last IP module access did time out.
03
Read
And
Write
Time Out Interrupt Enable
When set to “1”, this bit will enable the carrier
board to generate an interrupt upon time out of
an IP module access. The default setting or
reset condition is “0” (interrupt generation upon
time out disabled). The interrupt service
routine, in responding to the Time Out Access
interrupt, will need to set this bit to 0 to clear
the pending interrupt request.
02
Read
And
Write
IP Module Interrupt Enable
When set to “1”, this bit will enable the
generation of IP module interrupts. The default
setting or reset condition is “0” (IP module
interrupt generation disabled). Interrupts must
also be supported and configured at the IPs.
01
Read
Only
IP Module Interrupt Pending
This bit will be "1" when there is an interrupt
pending. This bit will be "0" when there is no
interrupt pending. Polling this bit will reflect the
IP Module’s pending interrupt status, even if
the IP Module Interrupt Enable bit is set to "0".
Reset condition: Set to "0".
00
Read
Only
IP Module Error
This bit will be "1" when there is an active IP
Module Error signal. This bit will be "0" when
all IP module Error signals are inactive. This
bit allows the user to monitor the Error signals
of IP modules A through E. The IP
specification states that the error signals
indicate a non-recoverable error from the IP
(such as a component failure or hard-wired
configuration error). Refer to your IP specific
documentation to see if the error signal is
supported and what it indicates. Reset
condition: Set to "0".
IP Interrupt Pending Register - (Read, P 02H)
The IP Interrupt Pending Register is used to individually
identify pending IP interrupts or a pending carrier generated
interrupt as a result of IP module time out access. If multiple IP
interrupts are pending, software must determine the order in
which they are serviced.
MSB
D7
D6
D5
D4
D3
D2
D1
LSB
D0
IP D
Int1
Pend
IP D
Int0
Pend
IP C
Int1
Pend
IP C
Int0
Pend
IP B
Int1
Pend
IP B
Int0
Pend
IP A
Int1
Pend
IP A
Int0
Pend
MSB
D15
D14
D13
D12
D11
D10
D9
LSB
D8
Not Used
(bits read as logic “0”)
Time Out
Interrupt
Pend
IP E
Int1
Pend
IP E
Int0
Pend
Where:
All Bits
IP Interrupt
Pending
(Read)
A bit will be a “1” when the corresponding
interrupt is pending. A bit will be a “0”
when its corresponding interrupt is not
pending. Polling this bit will reflect the IP
module’s pending interrupt status, even if
the IP interrupt enable bit is set to “0”.
Reset Condition: Set to "0". An IP
module pending interrupt bit will be
cleared if its correspond interrupt request
signal is inactive.
Clock Control Register - (Read/Write, P 018H)
The Clock Control Register is used to select the operational
frequency of the individual IP modules. A “0” (default) indicates
that the IP module is supplied with an 8MHz clock. A “1”
indicates that the IP module is supplied a 32MHz clock. A reset
will set all bits of this register to “0”.
MSB
D15 -- D5
D4
D3
D2
D1
LSB
D0
Not Used
IP E
CLK
IP D
CLK
IP C
CLK
IP B
CLK
IP A
CLK
IP Module Interrupt Space - (Read Only)
The Interrupt space for each IP module is fixed at two 16-bit
words. Interrupt 0 select space is read, typically by an interrupt
service routine, to respond to an interrupt request via the IP
Module’s INTREQ0* signal. Likewise interrupt 1 select space is
read to respond to an interrupt request via the IP Module’s
INTREQ1* signal. An access to an interrupt select space results
in the IP module serving up an interrupt vector. In addition,
access to the interrupt space will cause some IP modules to
release their interrupt request. See each IP module’s User
Manual for details.