AcroPack Series APCe7012E-LF
PCI Express Carrier Board
- 15 -
Table 4 Mini-PCIe Connector J1 Pin Assignments
Pin #
Name
Pin #
Name
51
+5V
3
52
+3.3V
4
49
+12V
3
50
GND
47
-12V
3
48
+1.5V
45
Present
46
N.C. (LED_WPAN#)
1
43
GND
44
N.C. (LED_WLAN#)
1
41
+3.3V
4
42
N.C. (LED_WWAN#)
1
39
+3.3V
4
40
GND
37
GND
38
N.C. (USB_D+)
1
35
GND
36
N.C. (USB_D-)
1
33
PETp0
34
GND
31
PETn0
32
SMB_DATA
5
29
GND
30
SMB_CLK
5
27
GND
28
+1.5V
25
PERp0
26
GND
23
PERn0
24
+3.3V
4
21
GND
22
PERST#
19
TDI
(UIM_C4)
1,2
20
N.C. (W_DISABLE#)
1
17
TDO
(UIM_C8)
1,2
18
GND
15
GND
16
N.C. (UIM_VPP)
1
13
RECLK+
14
N.C. (UIM_RESET)
1
11
REFCLK-
12
N.C. (UIM_CLK)
1
9
GND
10
N.C. (UIM_DATA)
1
7
CLKREQ#
8
N.C. (UIM_PWR)
1
5
TCK
(COEX2)
1
6
+1.5V
3
TMS
(COEX1)
1
4
GND
1
N.C. (WAKE#)
1
2
+3.3V
4
Notes (Table ):
1.
The following mini-PCIe signals are not supported: USB_D+, USB_D-, WAKE#,
LED_WPAN#, LED_WLAN#, LED_WWAN#, W_DISABLE#, COEX1, COEX2, UIM_C4,
UIM_C8, UIM_VPP, UIM_RESET, UIM_CLK, UIM_DATA, UIM_PWR. The following
signals UIM_C4, UIM_C8, COEX2 and COEX1 are repurposed for JTAG.
2.
TDI is tied to TDO on modules that do not use JTAG.
3.
+5, +12, and -12 Volt power supplies have been assigned to pins that are
reserved in the mini-PCIe specification. Remove the fuses on these power
supplies for mini-PCIe cards from other vendors that cannot tolerate power
applied to these reserved pins.
4.
All +3.3Vaux power pins are changed to 3.3V power.
5.
The SM bus signals SMB_CLK and SMB_DATA are used to communicate with a
CPLD on the carrier that reports slot ID. These signals will be under the control of
the AcroPack module.
PCI Express Bus Connections
Table 5 indicates the pin assignments for the PCIe bus signals at the card edge
connector P1. Connector pins are designated by a letter and a number. The
letter indicates which side of a particular connector the pin contact is on. “B”
