Acromag APCe7012E-LF User Manual Download

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AcroPack Series APCe7012E-LF

PCI Express Carrier Board

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is on the top (component) side of the carrier board while “A” is on the bottom

(solder) side. Connector “gold finger” numbers increase with distance from

the bracket end of the printed circuit board.

Refer to the PCI Express bus specification for additional information on the

PCI Express bus signals.

Table 5 PCIe Bus P1 CONNECTIONS

Signal

Pin

Signal

+12V

B01

A01

PRSNT1*

+12V

B02

A02

+12V

B03

A03

+12V

GND

B04

A04

GND

SMCLK

B05

A05

TCK

SMDAT

B06

A06

TDI

GND

B07

A07

TDO

+3.3V

B08

A08

TMS

TRST*

B09

A09

+3.3V

+3.3Vaux

B10

A10

+3.3V

WAKE*

B11

A11

PERST*

RSVD

B12

A12

GND

B13

A13

REFCLKp

Tx0p

B14

A14

REFCLKn

Tx0n

B15

A15

GND

B16

A16

Rx0p

N.C.

B17

A17

Rx0n

GND

B18

A18

GND

Notes (Table ):

Asterisk (*) is used to indicate an active-low signal.

BOLD ITALIC Logic Lines are NOT USED by the carrier board.

+3.3Vaux power to AcroPack is not used by the carrier. Contact Acromag to

3.3Vaux power to the AcroPack module. The carrier pr3.3V

power to the module.

JTAG Programming/Debug Connector

A JTAG programming/debug connector is provided for developing applications

that use Acromag’s FPGA AcroPack modules. See reference designator P3 in

Error! Reference source not found.

. This is a standard 14-pin Xilinx

programming header for connecting a Xilinx Platform USB II programming

device (or equivalent). The pin assignment for P3 is shown in Table . A CPLD

on the carrier is included in the JTAG chain. The Xilinx Vivado tools can detect

the presence of the CPLD in the JTAG chain and skip it when accessing the

FPGAs on the AcroPack modules.

Summary of Contents for APCe7012E-LF

Page 1: ...rd USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road Wixom MI 48393 2417 U S A Tel 248 295 0310 Email solutions acromag com Copyright 2019 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8501138B ...

Page 2: ...ware Support 5 Windows 5 VxWorks 5 Linux 6 2 PREPARATION FOR USE 7 UNPACKING AND INSPECTION 7 BOARD CONFIGURATION 8 Power and Cooling Considerations 8 Carrier Fuses 9 Isolation Considerations 9 Isolated Power 9 CARRIER ADDRESS ASSIGNMENT 9 ACROPACK MODULE INSTALLATION 10 FIELD GROUNDING CONSIDERATIONS 11 CONNECTORS 11 Front Panel Field I O Connectors 11 AcroPack Field I O Connector 11 Mini PCIe Co...

Page 3: ...OCEDURE 19 WHERE TO GET HELP 19 6 SPECIFICATIONS 20 PHYSICAL 20 Physical Configuration 20 Connectors 20 Isolation 20 Isolated Power 20 Power 20 Fuses 21 PCIe BUS COMPLIANCE 21 ENVIRONMENTAL 21 EMC Compliance 21 Vibration and Shock Standard 22 APCe7012E LF Reliability Prediction 22 7 CERTIFICATE OF VOLATILITY 23 8 REVISION HISTORY 23 ...

Page 4: ...requency Interference Statement This is a Class A product In a domestic environment this product may cause radio interference in which case the user may find it necessary to take adequate corrective measures Environmental Protection Statement This product has been manufactured to satisfy environmental protection requirements where possible Many components used structural parts circuit boards conne...

Page 5: ...em to the individual AcroPack modules Cable Model 5028 420 Round cable shielded SCSI 2 to CHAMP 0 8mm 2 meters long Termination Panel Model 5025 288 DIN rail mountable panel provides 68 screw terminals for universal field I O termination SCSI 3 connector Software Support The AcroPack series products require support drivers specific to your operating system Supported operating systems include Linux...

Page 6: ...ing of Linux software This software Model APSW API LNX is composed of Linux libraries for all AcroPack modules VPX I O board products and PCIe I O Cards The software is implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag AcroPack modules ...

Page 7: ...e fields unless the device is contained within its original manufacturer s packaging Be aware that failure to comply with these guidelines will void the Acromag Limited Warranty UNPACKING AND INSPECTION Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be pres...

Page 8: ...circulation must be provided to prevent a temperature rise above the maximum operating temperature The lack of air circulation within the computer chassis could be a cause for some concern Most if not all computer chassis do not provide a fan for cooling of add in boards The dense packing of the AcroPack modules to the carrier board alone results in elevated module and carrier board temperatures a...

Page 9: ...he field I O connections are not isolated from the PCIe bus Isolated Power The use of an optional isolated DC DC Converter is required for use with a few of Acromag s isolated AcroPack modules See Figure 1 for carrier board location allocated for the isolated DC DC converter The power supplies of one AcroPack site must be isolated from the power supplies of other AcroPack sites The separate isolat...

Page 10: ... AcroPack module cables termination panels and field wiring Refer to Figure 2 while reading this section To install first insert the edge of the AcroPack module into the carrier connector at an angle similar to that shown in the figure Next using a rocking motion while gently applying force to keep the edge of the board against the back of the carrier connector position the module such that the fi...

Page 11: ...Front Panel Field I O Connectors Field I O connections are made via a 68 pin 0 8 mm Champ cable connector mounted on the front panel The cable and termination panel or user defined terminations can be quickly mated to the field I O connector Pin assignments are defined by the installed AcroPack module AcroPack Field I O Connector The field side connector of AcroPack module mates to a Samtec SS5 50...

Page 12: ...rved isolation 23 23 Reserved isolation 7 26 26 Field I O 13 41 25 25 Field I O 14 28 28 Reserved isolation 27 27 Reserved isolation 8 30 30 Field I O 15 42 29 29 Field I O 16 32 32 Reserved isolation 31 31 Reserved isolation 9 34 34 Field I O 17 43 33 33 Field I O 18 36 36 Reserved isolation 35 35 Reserved isolation 10 38 38 Field I O 19 44 37 37 Field I O 20 40 40 Reserved isolation 39 39 Reserv...

Page 13: ...57 Field I O 30 60 60 Reserved isolation 59 59 Reserved isolation 16 62 62 Field I O 31 50 61 61 Field I O 32 64 64 Reserved isolation 63 63 Reserved isolation 17 66 66 Field I O 33 51 65 65 Field I O 34 68 68 Reserved isolation 67 67 Reserved isolation 18 70 70 Field I O 35 52 69 69 Field I O 36 72 72 Reserved isolation 71 71 Reserved isolation 19 74 74 Field I O 37 53 73 73 Field I O 38 76 76 Re...

Page 14: ... O 45 57 89 89 Field I O 46 92 92 Reserved isolation 91 91 Reserved isolation 24 94 94 Field I O 47 58 93 93 Field I O 48 96 96 Reserved isolation 95 95 Reserved isolation 25 98 98 Field I O 49 59 97 97 Field I O 50 100 100 Reserved isolation 99 99 Reserved isolation Mini PCIe Connector The AcroPack Mini PCIe connector mates to a TE Connectivity 1759457 1 connector on the carrier board Pin assignm...

Page 15: ...WPAN LED_WLAN LED_WWAN W_DISABLE COEX1 COEX2 UIM_C4 UIM_C8 UIM_VPP UIM_RESET UIM_CLK UIM_DATA UIM_PWR The following signals UIM_C4 UIM_C8 COEX2 and COEX1 are repurposed for JTAG 2 TDI is tied to TDO on modules that do not use JTAG 3 5 12 and 12 Volt power supplies have been assigned to pins that are reserved in the mini PCIe specification Remove the fuses on these power supplies for mini PCIe card...

Page 16: ... C B17 A17 Rx0n GND B18 A18 GND Notes Table 1 Asterisk is used to indicate an active low signal 2 BOLD ITALIC Logic Lines are NOT USED by the carrier board 3 3 3Vaux power to AcroPack is not used by the carrier Contact Acromag to enable 3 3Vaux power to the AcroPack module The carrier provides 3 3V power to the module JTAG Programming Debug Connector A JTAG programming debug connector is provided ...

Page 17: ...is pin is the serial data stream received from the TDO pin on the last device in a JTAG chain TDI JTAG Test Data In This pin outputs the serial data stream transmitted to the TDI pin on the first device in a JTAG chain 3 3V The target reference voltage VREF is 3 3 Volts GND Signal return 3 PROGRAMMING INFORMATION This APCe7012E LF carrier board has no end user programmable components 4 THEORY OF O...

Page 18: ... the carrier The CPLD will serialize the slot address and transmit the address to the AcroPack module as requested by the AcroPack module The processes of reading the slot address is typically initiated by host software See CARRIER ADDRESS ASSIGNMENT in section 2 for details regarding slot address selection JTAG A JTAG interface is provided for programming and debugging FPGAs on AcroPack modules I...

Page 19: ...sure that all of the procedures in Section 0 PREPARATION FOR USE have been followed Also refer to the documentation of your carrier board to verify that it is correctly configured Verify that there are no blown fuses Replacement of the carrier and or AcroPack with one that is known to work correctly is a good technique to isolate a faulty board WHERE TO GET HELP If you continue to have problems yo...

Page 20: ...he field I O connections are not isolated from the PCIe bus Host logic and field I O are isolated from each other for voltages up to 250VAC or DC on a continuous basis unit will withstand a 1500V AC dielectric strength test for one minute without breakdown The carrier is designed to be used with isolated AcroPack modules Due to the spacing between the pads of the 68 pin Champ connector and cable t...

Page 21: ... Refer to your system documentation for more information on PCIe power specifications Fuses 1 5 1 1 Amps F6 Raychem NANOSMDC110F 2 3 3V 3 Amps F4 Littelfuse 0466003 NR 5V 12V 12V 2 Amps F1 F2 F3 Littelfuse 0453002 MR PCIe BUS COMPLIANCE Specification This device meets or exceeds all written PCI Express specifications per revision 2 1 ENVIRONMENTAL Operating Temperature 40 to 85 C with 200 LFM airf...

Page 22: ...ed to comply with IEC 60068 2 64 10 500Hz 5G rms 2 Hours axis Shock Operating Designed to comply with IEC 60068 2 27 30G 11ms half sine 50G 3mS half sine 18 shocks at 6 orientations for both test levels APCe7012E LF Reliability Prediction MTBF Mean Time Between Failure MTBF in hours using MIL HDBK 217F FN2 Per MIL HDBK 217 Ground Benign Controlled GBGC Temperature MTBF Hours MTBF Years Failure Rat...

Page 23: ...latile Memory Does this product contain Non Volatile memory i e Memory of whose contents is retained when power is removed Yes No Acromag Representative Name Russ Nieves Title Director of Sales and Marketing Email rnieves acromag com Office Phone 248 295 0838 Office Fax 248 624 9234 8 REVISION HISTORY The following table shows the revision history for this document Release Date Version EGR DOC Des...

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