Acromag IOS-EP201, User Manual

Page 1: ... Modules USER S MANUAL ACROMAG INCORPORATED Tel 248 295 0310 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Wixom MI 48393 7037 U S A solutions acromag com Copyright 2009 2011 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 853 B11C007 ...

Page 2: ...ion Considerations 8 3 0 PROGRAMMING INFORMATION CONFIGURATION MODE 9 Configuration Address Map 9 Configuration Registers 10 Configuration Methodologies Procedures 10 IOS Identification Space 12 USER MODE 13 Example Design Address Map 13 Control Register 15 Input Output Registers 15 Direction Control Registers 16 Interrupt Enable Register 17 Interrupt Type Configuration Register 17 Interrupt Statu...

Page 3: ... SPECIFICATIONS PHYSICAL 29 ENVIRONMENTAL 29 BOARD COMPONENTS 30 DIFFERENTIAL INPUT OUTPUT 30 DIGITAL INPUT OUTPUT 31 LVDS INPUT OUTPUT 31 EXTERNAL CLOCK INPUT 32 POWER ON RESET 32 DRAWINGS IOS EP2 BLOCK DIAGRAM 33 JTAG INTERFACE JUMPER LOCATION 34 RS485 I O CONNECTIONS 34 The following manuals and part specifications provide the necessary information for in depth understanding of the IOS EP2 Seri...

Page 4: ... FGPA Important Note The following IOS models are accessories to the IOS Server Models IOS 7200 IOS 7200 WIN IOS 7400 and IOS 7400 WIN which are cULus Listed This equipment is suitable for use in Class I Division 2 Groups A B C and D or non hazardous locations only MODEL TTL Channels EIA 485 422 Channels LVDS Channels Operating Temperature Range IOS EP201 48 0 0 40 to 85 C IOS EP202 0 24 0 40 to 8...

Page 5: ...cromag provides an engineering design kit for the IOS EP2 Series boards sold separately a must buy for first time IOS EP2 module purchasers The design kit model IOS EP2 EDK provides the user with the basic information required to develop a custom FPGA program for download to the Altera FPGA The design kit includes a CD containing schematics parts list part location drawing example VHDL source and ...

Page 6: ...terial be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the board be visually inspected for evidence of mishandling prior to applying power Power should be removed from the board when installing IOS modules cables termination pan...

Page 7: ...DS defined by the IOS EP2 model Table 2 2 lists the channels dedicated to each of the IOS EP2 models Pin Description Pin Number Pin Description Pin Number DIFF 1 TTL DIFF 1 TTL I O00 I O00 1 I O12 I O25 26 I O00 I O01 2 I O13 I O26 27 I O01 I O02 3 I O13 I O27 28 I O01 I O03 4 I O14 I O28 29 I O02 I O04 5 I O14 I O29 30 I O02 I O05 6 I O15 I O30 31 I O03 I O06 7 I O15 I O31 32 I O03 I O07 8 I O16 ...

Page 8: ...be used for global input signals for each IOS EP2 Series model Note that modification of the example vhdl file is required to utilize the additional global inputs Model Buffered Global Inputs 1 IOS EP201 TTL Channels 18 22 46 IOS EP202 RS485 Channels 9 11 23 IOS EP203 TTL Channels 18 22 RS485 Channel 23 IOS EP204 LVDS Channels 9 11 23 The board is non isolated since there is electrical continuity ...

Page 9: ...he status configured vs non configured of the FPGA This signal must be held low by the Altera FPGA after successful configuration to disable configuration mode If you have a configured FPGA and then wanted to re configure the FPGA you must enable the configuration mode This is accomplished by driving pin F3 of the FPGA to a logic high level via control register bit 0 If you change your mind and wa...

Page 10: ...ogic 1 to bit zero of the Configuration Control Status Register Then after bit 0 of the Configuration Control Status register reads logic low again up to 160mS the programming file is written to this register one byte at a time The data is transferred serially to the FPGA therefore a write to this register requires 8 wait states The IOS EP2 module has three methods of configuration The first is co...

Page 11: ...d high for up to 160 seconds after the control bit is set high 6 The status of the Altera FPGA during configuration can be monitored via the Status register at base address 00H Bit 1 monitors the Altera nStatus signal which must remain high during configuration Bit 2 of the Status register reflects the Altera FPGA CONF_DONE signal The CONF_DONE signal must remain at a logic low until configuration...

Page 12: ... Refer to the documentation provided with the IOS EP2 EDK for further instructions on JTAG configuration Each IOS module contains identification ID information that resides in the ID space per the IOS module specification This area of memory contains at most 32 bytes of information Both fixed and variable information may be present within the ID space Fixed information includes the IOS identifier ...

Page 13: ...ra interface to the clock generator chip and I O interface to differential or TTL I O The IOS EP2 Series hardware supports a direct connection to all IOS bus signals as listed in Table 2 4 As such hardware will support all IOS bus cycles including ID I O Interrupt Memory and DMA The example design provided uses all but the Memory and DMA cycle types The I O space address map for this example desig...

Page 14: ...Control Register 08 0B Not Used 2 Interrupt Enable Register 0A 0D Not Used 2 Interrupt Type Register 0C 0F Not Used 2 Interrupt Status Register 0E 11 Not Used 2 Interrupt Polarity Register 10 13 Not Used 2 Interrupt Vector Register 12 15 Memory Data Register 14 17 Memory Address Register 16 19 Clock Control Register 1 18 1B Clock Control Register 2 1A 1D Not Used 2 Clock Control Register 3 1C 1F N...

Page 15: ...el corresponding to your IOS EP2 Control Register Bits 10 9 and 8 IOS Model Bit 10 Bit 9 Bit 8 Disabled 0 0 0 IOS EP201 1 1 1 IOS EP202 0 0 1 IOS EP203 1 0 0 IOS EP204 0 0 1 Bit 11 is reserved for factory testing For normal operation this bit should always be logic low Bit 15 can be used to issue a software reset When bit 15 is set to a logic high a software reset will occur Reading this register ...

Page 16: ...he lower ordered bits corresponding to the lower numbered channels for the register of interest All input output channels are configured as inputs on a power on or software reset The unused upper bits of these registers will always read logic 0 Direction Control Register Read Write Base Addr 08H The data direction input or output of the digital I O channels is selected via this register The data d...

Page 17: ...ng input channel to generate an interrupt Only those channels enabled for interrupts will generate interrupts Interrupts are only available on the first eight channels Interrupt Enable Register MSB LSB Bit 07 Bit 06 Bit 05 Bit 04 Bit 03 Bit 02 Bit 01 Bit 00 Ch 07 Ch 06 Ch 05 Ch 04 Ch 03 Ch 02 Ch 01 Ch 00 The Interrupt Enable register at the carrier s base address offset 0AH is used to control chan...

Page 18: ...or the corresponding channel A channel that does not have interrupts enabled will never set its interrupt status flag A channel s interrupt can be cleared by writing a 1 to its bit position in the Interrupt Status Register writing a 1 acts as a reset signal to clear the set state This is known as the Release On Register Access RORA method as defined in the VME system architecture specification How...

Page 19: ...upt Vector Register maintains an 8 bit interrupt pointer for all channels configured as input channels The Vector Register can be written with an 8 bit interrupt vector This vector is provided to the carrier and system bus upon an active INTSEL cycle Reading or writing to this register is possible via 16 bit or 8 bit data transfers Interrupts are released on register access to the Interrupt Status...

Page 20: ...it state A software or hardware reset will clear this register to zero Clock Control Reg 1 Read Write Base 18H The Clock Control Register 1 is a 16 bit read write register This is used as part of the control for the Cypress CY22150 Programmable Clock The register contains the following control bits as specified in the Cypress CY22150 spec sheet Bit Data Bit Data D0 DIV1N 0 D8 Q 0 D1 DIV1N 1 D9 Q 1...

Page 21: ...1EH The Clock Trigger Register is an 8 bit register To initiate programming of the Cypress CY22150 Programmable Clock with the values set in Clock Control Registers 1 2 and 3 write a 1 to bit 0 of this register During programming bit 0 will remain logic high The programming process takes approximately 1 2ms to complete after the initial trigger A software or hardware reset has no affect on this re...

Page 22: ... generate interrupts for the following conditions Change of State COS at selected input channels Input level polarity match at selected input channels Interrupts generated by the IOS EP2 use interrupt request line INTREQ0 Interrupt Request 0 The interrupt release mechanism employed is the Release On Register Access RORA type This means that the interrupter will release the I O Server Module interr...

Page 23: ...sition Processing Change of State Interrupts 1 Clear the interrupting channel s by writing a 1 to the appropriate bits in the IOS EP20X Interrupt Status Register Programming Example for Level Polarity Match Interrupts 1 Select channel Polarity Match Interrupts by writing a 0 to each channel s respective bit in the Interrupt Type Register Note that Change Of State interrupts specified with 1 may be...

Page 24: ...nterrupt service routines to service individual IOS modules 3 The carrier board interrupt service routine accesses the interrupt space of the IOS module selected to be serviced Note that the interrupt space accessed must correspond to the interrupt request signal driven by the IOS module 4 The carrier board will assert the INTSEL signal to the appropriate IOS module together with carrier board gen...

Page 25: ...arrier to IOS module interface allows access to both ID and I O space via 16 or 8 bit data transfers Read only access to ID space provides the identification for the individual module as given in Table 3 2 per the IOS specification Read and write accesses to the I O space provide a means to control the IOS EP2 The IOS EP2 has 64K words of SRAM available Read and write accesses to the SRAM are impl...

Page 26: ...ential I O are provided on the IOS EP202 and IOS EP203 models through the Field I O Connector refer to Table 2 1 and 2 2 Differential channels to the FPGA are buffered using EIA RS485 RS422 line transceivers The transceivers are considered failsafe as a open or short circuit on the I O will not damage the board Field input lines are not terminated External 120 Ohm resistors are recommended on all ...

Page 27: ...GA signals utilized are 16 data lines DATA0 to DATA15 and six address lines A 1 to 6 The many control lines that comprise the IOS bus include IOS Reset nIOsel nIDsel nMEMsel nINTsel R_nW nAck nIntReq0 nIntReq1 nDMAReq0 nDMAReq1 nDMAAck nDMAend nStrobe nBS0 and nBS1 A complete listing of the IOS interface pins and their assignment on the Cyclone II FPGA is available in the IOS EP2 EDK The IOS bus 8...

Page 28: ...s automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair Before beginning repair be sure that all of th...

Page 29: ...sed 1 Monotonic ramp up required with 100ms maximum rise time 2 Typical operating amperage assumes of I O is driving a standard load Operating Temperature 40 C to 85 C Relative Humidity 5 95 Non Condensing Storage Temperature 55 C to 125 C Non Isolated Logic and field commons have a direct electrical connection Radiated Field Immunity RFI Complies with EN61000 4 3 3V m 80 to 1000MHz AM 900MHz keye...

Page 30: ...alent Generate Frequencies from 250kHz to 100MHz Channel Configuration 24 IOS EP202 or 12 IOS EP203 Bi directional EIA 485 422 differential signals are direction controlled in groups of four 1 5 V Min 3 3V Max Differential Driver Output Voltage with 54 load 3 V Max Common Mode Output Voltage 0 2 Min to 0 05 Max Differential Input Threshold Voltage 7V VCM 12V 15mV Typical Input Hysteresis 96K Minim...

Page 31: ...ll down resistors to GND are installed on each Digital I O line Channel Configuration 24 Channels IOS EP204 Bi directional LVDS signals are direction controlled in groups of 4 247mV Min 454mV Max LVDS Driver Output Voltage with 50 load 1 37 V Max Common Mode Output Voltage 50 mV Min to 50mV Max LVDS Input Threshold Voltage Compatible with either LVDS TIA EIA 644 or M LVDS TIA EIA 899 for Multipoin...

Page 32: ...ectrical Characteristics VIN 3 3V Maximum VIL 0 8V Maximum VIH 1 7V Minimum Power On Delay The IOS EP2 has a power up time of 0 3 seconds During this time the IOS module will not respond to any request After this initial power on reset another 0 4 seconds maximum is required if loading the FPGA from FLASH During this time the board will act as if it is not configured until the download to the FPGA...

Page 33: ... Module ___________________________________________________________________ __________________________________________________________________________ Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 33 ...

Page 34: ...A Module __________________________________________________________________ __________________________________________________________________________ Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 34 ...