IOS-EP2 I/O SERVER MODULE Cyclone II Based FPGA Module
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Table 3.5 shows all channels and their corresponding I/O data register
bit for each of the IOS-EP2 models. The register bits not listed will not be
used. See the memory map to identify the addresses required to control I/O
registers.
Used Input/Output Channel Register Bits
Model
I/O Register Bits
See Table 2.1 for Pin Assignments
IOS-EP201
TTL Channels 0 to 47
Register Bits 0 to 47
IOS-EP202
Differential/RS485 Channels 0 to 23
Register Bits 0 to 23
IOS-EP203
TTL Channels 0 to 23
Register Bits 0 to 23
Diff./RS485 Channels 12 to 23
Register Bits 32 to 43
IOS-EP204
LVDS Channels 0 to 23
Register Bits 0 to 23
Channel read/write operations use 8-bit, or 16-bit data transfers with the
lower ordered bits corresponding to the lower-numbered channels for the
register of interest. All input/output channels are configured as inputs on a
power-on or software reset. The unused upper bits of these registers will
always read logic “0”.
Direction Control Register (Read/Write) - (Base Addr +08H)
The data direction (input or output), of the digital I/O channels, is
selected via this register. The data direction of all differential channels are
set as a group of two or four channels while data direction of all TTL
channels is controlled as a group of 8 channels. Setting a bit high
configures the data direction, for the identified channels, as output. Setting
the control bit low config
ures the corresponding channel‟s data direction for
input. Refer to Table 3.6 for the corresponding channels for each bit in the
Direction Control Register.
The default power-up state of these registers is logic low. Thus, all
channels are configured as inputs on system reset or power-up. All not
used bits will read low logic. See Table 2.1 for field I/O pin assignments
corresponding to each of the Differential and TTL channels listed below.
USER MODE
Table 3.5:
Input/Output
Register Module Mapping
