IOS-EP2 I/O SERVER MODULE Cyclone II Based FPGA Module
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Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com
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The IOS-EP2 series allows interface with a mix of up to 48 TTL I/O
channels or up to 24 differential I/O signals. The signals DIO(0) to DIO(47)
are utilized for digital input/output control to the field signals. The six signals
DIFF_DIR(0-5) control data direction of the 24 differential I/O signals. The
six signals TTL_DIR_BANK(1-6) control data direction of the 48 TTL I/O
channels. Digital Field inputs are 5V tolerant. An additional External Clock
input is available on all models. This input is not buffered and requires
LVTTL signaling levels.
Digital TTL field I/O are provided on the IOS-EP201 and IOS-EP202
models through the Field I/O Connector (refer to Table 2.2). Digital
input/output signals to the FPGA are buffered using an octal bus
transceiver. Signals received are converted from 5V TTL to LVTTL as
required by the FPGA. The digital receivers output TTL signals. The
direction control of the digital channels is controlled in groups of eight.
Each field line has a 10K pull-down resistor to GND. Output operation is
considered „Fail-safe‟. That is, the Digital Input/Output signals are always
configured as inputs following a power-up or software reset. This is done for
safety reasons to ensure reliable control under all conditions.
Differential I/O are provided on the IOS-EP202 and IOS-EP203 models
through the Field I/O Connector (refer to Table 2.1 and 2.2). Differential
channels to the FPGA are buffered using EIA RS485/RS422 line
transceivers. The transceivers are considered failsafe as a open or short
circuit on the I/O will not damage the board. Field input lines are not
terminated.
External 120 Ohm resistors are recommended on all
receivers.
Signals received are converted from the required EIA
RS485/RS422 voltages to the LVTTL levels required by the FPGA.
Likewise, LVTTL signals are converted to the EIA RS485/RS422 voltages
for data output transmission. The direction control of the differential
channels is controlled in groups of four.
LVDS I/O on the IOS-EP204 are provided through the Field I/O
Connector (refer to Table 2.3). LVDS channels (0-31) to the FPGA are
buffered using multidrop LVDS line drivers and receivers. The drivers and
receivers are standard LVDS signaling characteristics (TIA/EIA-644) with
double the current for multipoint applications. Field inputs to these receivers
include a 100 ohm termination resistor. Signals received are converted from
the LVDS voltages to the LVTTL levels required by the FPGA. Likewise,
LVTTL signals are converted to the TIA/EIA-644 LVDS voltages for data
output transmission. The direction control of the LVDS channels is
controlled in groups of four.
The IOS-
EP2 Series operation is considered „Fail-safe‟. That is, the
input/output channels are always configured as input upon power-up reset,
and a system software reset. This is done for safety reasons to ensure
reliable control of the output state under all conditions.
Digital Input/Output Logic
EIA-RS485/RS422
Input/Output Logic
LVDS Input/Output Logic
Fail-Safe Operation
