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Series IP503 Industrial I/O Pack

EIA/TIA-232E & Centronics Communication Module

USER’S MANUAL

ACROMAG INCORPORATED

30765 South Wixom Road

P.O. BOX 437

Wixom, MI 48393-7037 U.S.A.

Tel: (248) 624-1541

Fax: (248) 624-9234

Copyright 1995, Acromag, Inc., Printed in the USA.

Data and specifications are subject to change without notice.

8500-539-B98G009

Summary of Contents for Series IP503

Page 1: ...tion Module USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 1995 Acromag Inc Printed in the USA Data and spe...

Page 2: ...toring system This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall system design It is agreed between the Buyer...

Page 3: ...m performance with precision analog I O applications The X suffix of the model number denotes the length in feet Model 5029 944 IP503 Serial Communication Cable A 5 foot long flat 50 pin cable with a...

Page 4: ...n assignments are unique to each IP model see Table 21 and normally correspond to the pin numbers of the field I O interface connector on the carrier board you should verify this for your carrier boar...

Page 5: ...ground to safety ground via any device connected to these ports or a ground loop will be produced and this may adversely affect operation The communication cabling of the P2 interface carries digital...

Page 6: ...ing Little Endian uses even byte addresses to store the low order byte As such use of this module on an ISAbus PC AT carrier board will require the use of the even address locations to access the 8 bi...

Page 7: ...transmitted then data is right justified to the LSB If parity is used then LCR bit 3 parity enable and LCR bit 4 type of parity are required Status for the receiver is provided via the Line Status Reg...

Page 8: ...gh to low transition start bit When the start bit is detected a counter is reset and counts the 16x sampling clock to 7 1 2 which is the center of the start bit The receiver then counts from 0 to 15 t...

Page 9: ...NOT supported by this model FIFO Control Register FCR BIT FUNCTION 0 When set to 1 this bit enables both the Tx and Rx FIFO s All bytes in both FIFO s can be cleared by resetting this bit to 0Data is...

Page 10: ...m Control Register 1 MCR Bit 4 provides a local loopback feature for diagnostic testing of the UART channel When set high the UART serial output connected to the TXD driver is set to the marking logic...

Page 11: ...d by a read of the IIR Line Status Register continued LSR Bit FUNCTION PROGRAMMING 6 Transmitter Empty TEMT 0 Not Empty 1 Transmitter Empty set when both the Transmitter Holding Register THR and the T...

Page 12: ...data lines This register is either output only or bi directional depending on the state of the extended mode bit bit 0 of the LEM register and the data direction control bit bit 5 of the LPC register...

Page 13: ...interrupt source the ACKN line of the parallel port or bit 2 of the LPS register The serial ports and the parallel port interrupts drive INTREQ0 Bit 0 of this register drives the ENIRQ line of the UA...

Page 14: ...atus of each channel can be read by the host CPU at any time during operation Two registers are used to report the status of a serial channel the Line Status Register LSR and the Modem Status Register...

Page 15: ...s the last stop bit time when the following occurs Bit 5 of the LSR THRE is 1 and there is not a minimum of two bytes at the same time in the transmit FIFO since the last time THRE 1The first transmit...

Page 16: ...Divisor Latch Access bit to permit access to the two divisor latch bytes used to set the baud rate These bytes share addresses with the Receive and Transmit buffers and the Interrupt Enable Register...

Page 17: ...puters are considered DTE devices while modems are DCE devices The EIA TIA 232E interface is the fifth revision of this standard and defines an unbalanced single ended transmission standard for unidir...

Page 18: ...ver a null modem cable connection is required to connect two like configured DTE ports due to the imbalance of drivers and receivers see Drawing 4501 572 Pins 1 18 of field I O connector P2 provide co...

Page 19: ...S INPUT BUSY Pin 11 Input Line Printer Busy Active high signal from the printer that is asserted when the printer is not ready to accept more Data The state of this bit is monitored via Bit 7 of the L...

Page 20: ...o obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation o...

Page 21: ...t maximum Choose shielded or unshielded cable according to model number The unshielded cable is recommended for digital I O while the shielded cable is recommended for optimum performance with precisi...

Page 22: ...Boards Application This panel converts the high density ribbon cable connectors coming from the APC8600 carrier board Acromag cable Model 5029 900 to screw terminals for direct wired interfaces This p...

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