VPX4812/4814
User’s Manual
Single-Slot 3U VPX Bus XMC Carrier Card/Switch Card Module
Acromag, Inc. Tel: 248-295-0310 - 16 - www.acromag.com
SW4-1:3
–
Upstream NT Port Selection
Switch Position
Selected NT Upstream Port
1
2
3
ON
ON
ON
VPX Fat Pipe A
ON
OFF
ON
VPX Fat Pipe B
OFF
OFF
OFF
NT Mode Disabled (default)
Note:
In addition to the switch configuration, there are settings for the PEX8624 that must be programmed to the on-
board EEPROM device to enable Non-Transparent Mode.
SW4-4
(SYSTEM CLOCK
SELECT)
ON
(Common)
Uses the 100MHz reference clock pins on the
VPX bus generated by the CPU board for PCIe timing. (Pins
E8 & F8 on the VPX P0 connector)
OFF (default)
(Non-Common)
Uses the 100MHz reference clock
generated on board for PCIe timing.
Note:
Best system stability may be achieved with the use of a 100MHz common clock connection from the SBC,
especially at Gen 2.0 link speeds. If the system does not provide a common clock, then non-common clock mode must
be used.
SW5
(JTAG VREF
SELECT)
1-2 (default)
JTAG_VREF = +3.3V
2-3
JTAG_VREF = +2.5V
4-5
Unused
5-6
Unused
