Operation Theory
37
edge of ADC sampling clock after the trigger condition was
met.
When the count reaches 0, the counter stops and PCI-9812/10
starts to acquire data.
Figure 5-4: Delay Trigger Acquisition
5.4 A/D Clock Source Control
The AD clock source determines how the board regulates the
timing of conversions when acquiring multiple samples from a
single channel or from a group of multiple channels. The A/D clock
sources on the PCI-9812 must use a pacer clock but not single
shot as the A/D converters are in a pipelined structure, which
require eight conversion clocks to complete the conversion of
digital data.
A/D Clock Sources
The A/D converters operate under the paced mode, which uses
pacer clock for A/D conversion at a fixed rate. PCI-9812/10
supports three clock sources for analog input conversion:
X
Internal A/D pacer clock (default);
X
External sine wave clock;
X
External square clock.
These three clock sources are described below:
Internal Pacer Clock
An onboard timer / counter is used as the internal A/D pacer clock.
The frequency of the pacer is software controllable. The maximum
pacer signal rate is 40Mz/2=20MHz, that is also the maximum
sampling rate of PCI-9812/10. Note that 40MHz is the onboard
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