Chapter 4. T1 Network Interface
61200610L2-1
TSU 610 User Manual
4-31
Board level tests
Each of the TSU 610 boards contain an on-board processor
which executes a series of tests checking the circuitry on the
board.
•
RAM tests; EPROM checksum
•
DS0 map tests
•
On-board data path; sending a known test pattern
through an on- board loop
Unit level tests
•
Front panel LED verification
•
Phase Lock Loop verify
•
Board-to-board interface test
A test pattern is sent from the controller through a loopback
on all other boards and is checked on the controller. This
verifies the data path, clocks, and control signals.
If a failure is detected, note the failure number and contact
ADTRAN Technical Support.
The execution of self-test will disrupt normal data flow and
prevent remote communication until the self-test is
completed.
Port Tests
The Port Tests menu is used to activate testing of specific data
ports. It controls the activation of loopbacks and the
initiation of data test patterns. Test results are displayed in
the LCD window.
The execution of Port Tests will disrupt normal data flow in
the port being tested.
Cancel Tests
Use this menu selection to deactivate all active tests,
including tests on option modules.
Summary of Contents for 1200610L2
Page 20: ...Table of Contents xx TSU 610 User Manual 61200610L2 1...
Page 24: ...List of Tables xxiv TSU 610 User Manual 61200610L2 1...
Page 56: ...Chapter 3 Operation 3 12 TSU 610 User Manual 61200610L2 1...
Page 94: ...Chapter 4 T1 Network Interface 4 38 TSU 610 User Manual 61200610L2 1...
Page 142: ...Appendix B Understanding TR 08 B 4 TSU 610 User Manual 61200610L2 1...
Page 156: ...Appendix E Specifications E 4 TSU 610 User Manual 61200610L2 1...
Page 168: ......
