Chapter 7 Test Menu
TSU LT User Manual
52
© 2003 ADTRAN, Inc.
61203060L1-1A
The self-test includes the following board-level tests, in this order:
1. RAM tests; EPROM checksum
2. On-board data path; sending a known test pattern through an on-board loop
3. Front panel LED verification
4. Phase lock loop verification. If a failure is detected, note the failure number and contact ADTRAN
Technical Support.
PORT TESTS
These two tests (
DTE L
OOPBCK
and
D
ATA
L
OOPBCK
) control the activation of a DTE loopback and a data
loopback (see Figure 7-4). The
DTE L
OOPBK
loops data received at the V.35 interface back towards the
DTE. The
D
ATA
L
OOPBACK
test the data is looped back just before going out the V.35 interface.
Figure 7-4. Port Loopback Tests
Executing self-test disrupts normal data flow and prevents remote communication until the
self-test is completed (approximately five seconds).
(NI)
Summary of Contents for TSU LT
Page 1: ...TSU LT USER MANUAL Part Number 1203060L1 61203060L1 1A April 2003...
Page 16: ...List of Figures TSU LT User Manual 16 2003 ADTRAN Inc 61203060L1 1A...
Page 18: ...List of Tables TSU LT User Manual 18 2003 ADTRAN Inc 61203060L1 1A...
Page 26: ...Chapter 2 Inspection and Installation TSU LT User Manual 26 2003 ADTRAN Inc 61203060L1 1A...
Page 34: ...Chapter 3 Operation TSU LT User Manual 34 2003 ADTRAN Inc 61203060L1 1A...
Page 38: ...Chapter 4 Status Menu TSU LT User Manual 38 2003 ADTRAN Inc 61203060L1 1A...
Page 58: ...Appendix B DTE Data Rate Chart TSU LT User Manual 58 2003 ADTRAN Inc 61203060L1 1A...
Page 62: ...Appendix C Pinouts TSU LT User Manual 62 2003 ADTRAN Inc 61203060L1 1A...