Copyright
2017
Advantech Co. Ltd. All rights reserved.
Page 59
JTAG
Joint Test Action Group
LAN
Local Area Network
LPC
Low Pin Count
MAC
Media Access Control
MDIO
Management Data Input / Output Interface over MDC/MDIO lines
MTBF
Mean Time Between Failure
NC‐SI
Network Controller Sideband Interface
NMC
Network Mezzanine Card
PCI
Peripheral Component Interconnect Local Bus
PCIe
PCI Express.
PCH
Platform Controller Hub
PECI
Platform Environment Control Interface.
PET
Platform Event Trap.
PHY
Physical Layer Device
PICMG
PCI Industrial Computer Manufacturers Group
QPI
Quick Path Interconnect. A cache‐coherent, link‐based interconnect
specification for Intel Processors, chipsets, and I/O bridge.
RAID
Redundant Array of Inexpensive Disks or Redundant Array of Independent Disks
RANK
A unit of DRAM corresponds to four to eight devices in parallel, ignoring ECC.
These devices are usually, but not always, mounted on a single side of a DDR3
DIMM.
RDIMM
Registered dual In‐line Memory Module.
RGMII
Reduced gigabit media independent interface
RTC
Real Time Clock
Sandy Bridge‐EP
Processor
Intel’s 32‐nm processor design, follow‐on to the 32‐nm Sandy Bridge processor
design.
SATA
Serial ATA.
SAS
Serial Attached SCSI
SCI
System Control Interrupt. Used in ACPI protocol.
SDRAM
Synchronous Dynamic Random Access Memory
SerDes
Serializer and De‐Serializer Circuit
SGMII
Serialized Gigabit Media Independent Interface
SIU
Serial I/O Unit
SIW
Serial I/O and Watchdog Timer
SKU
Stock Keeping Unit
