87
0 Disable
1 Enable
ONE/FH
Interrupt source bit
0 Interrupt when an A/D conversion occurs
1 Interrupt when the FIFO is half full.
CNT0
Counter 0 clock source select bit
0 The clock source of Counter 0 comes from the
internal clock, 1 MHz
1
The clock source of Counter 0 comes from the
external clock, maximum up to 10 MH
AD16/12
Analog Input resolution.
0 16 bit
1 12 bit. And those two registers BASE+0 &
BASE+1 (
Table C-7
)
Table C-7: MIC-3716 Register for channel number and
A/D data
Read
Channel Number and A/D Data
Bit #
7
6
5
4
3
2
1
0
BASE + 1
CH3
CH2
CH1
CH0
AD11
AD10
AD9
AD8
BASE + 0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
AD11 ~ AD0
Result of A/D Conversion
AD0
the least significant bit (LSB) of A/D
data
AD11
the most significant bit (MSB)
Summary of Contents for MIC-3716
Page 2: ...ii This page is left blank for hard printing...
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Page 8: ...viii Table E 2 D A binary code table 117...
Page 11: ...1 Introduction 1 CHAPTER...
Page 17: ...7 Fig 1 1 Installation Flow Chart...
Page 21: ...11 Installation and Configuration CHAPTER 2...
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Page 41: ...31 Signal Connections CHAPTER 3...
Page 44: ...34 Fig 3 1 I O connector pin assignments for the MIC 3716...
Page 50: ...40...
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Page 55: ...45 Software Programming Overview CHAPTER 4...
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Page 61: ...51 Calibration CHAPTER 5...
Page 77: ...67 Appendixes...
Page 81: ...71 Appendix B Block Diagrams...
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