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PAC-4010 User Manual V1.0 Copyright 2016 Advantech Co. Ltd. All rights reserved. Page
107
Table 6-22: Configuration Mode Sensor Event Data Format
Event Direction Event Data 1
Event Data 2
Event Data 3
[7] =
0b (Assertion)
[7:4] = 8h (OEM code
in Event Data 2,
unspecified Event
Data byte 3),
[3:0]: State
De-/Asserted
[7:4] = 0h
[3:0] = DIP switch bits
FFh
(unspecified)
State asserted (offset 01h) means that one of the configuration DIP switch bits is set
and state deasserted (offset 00h) means all are off. The full DIP switch bit mask [3:0] is
provided by the sensor reading and in the event data2 byte.
6.4.2.11 IPMC Power Supply Sensor
An IPMI Power Supply sensor is provided to allow the detection of single voltage rail
fails. The single voltage power good signal states are retrieved from FPGA (register
interface) and used for this power good sensor.
The sensor generates an event in case of voltage failures, to facilitate the power fail
analysis, with below defined event data format.
Table 6-23: IPMC Power Good Sensor Event Data Format
Event
Direction
Event Data 1
Event Data 2
Event Data 3
[7] =
0b (Assertion)
[7:4] = 8h (OEM code in
Event Data 2, unspecified
Event Data byte 3),
[3:0]: Specific Offset
Voltage Index
(see table below)
FFh
(unspecified)
Only one event is used for this sensor:
Table 6-24: IPMC Power Good Sensor Supported Events
Sensor Type
Type
Code
Specific
Offset
Event
Power Supply
08h
01h
Power Supply Failure detected
Event data byte 2 for this sensor provides a byte value with a Power Good ID number
which correspondents to a single board voltage or power good signal as specified in
table.
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