37
C.6 Interrupt control register — BASE+20H
Table C-5 PCI-1784 Register for interrupt control
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Base Addr.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Interrupt control
DI3
DI2
DI1
DI0
IX3
IX2
IX1
IX0
UN3
UN2
UN1
UN0
OV3
OV2
OV1
OV0
20H W
IE
TM
UC3
UC2
UC1
UC0
OC3
OC2
OC1
OC0
OV
n
Interrupt by overflow bit (
n
: 0 ~ 3)
0
Disable
1
Enable
UN
n
Interrupt by underflow bit (
n
: 0 ~ 3)
0
Disable
1
Enable
IX
n
Interrupt by index status bit (
n
: 0 ~ 3)
0
Disable
1
Enable
DI
n
Interrupt by digital input bit (
n
: 0 ~ 3)
0
Disable
1
Enable
OC
n
Interrupt by counter over compare bit (
n
: 0 ~ 3)
0
Disable
1
Enable
UC
n
Interrupt by counter under compare bit (
n
: 0 ~ 3)
0
Disable
1
Enable
TM
Interrupt by timer pulse bit
0
Disable
1
Enable
IE
Overall interrupt enable bit
0
Disable
1
Enable