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PCA-6154/6154L User's Manual
4.1.4 CHIPSET features setup
By choosing the “CHIPSET FEATURES SETUP” option from the
INITIAL SETUP SCREEN Menu, the screen below is displayed. This
sample screen contains the manufacturer’s default values for the
PCA-6154/6154L.
ROM PCI/ISA BIOS (2A5IIAKB)
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
Figure 4-4: CHIPSET features setup screen
VGA Shared Memory Size
Share memory architecture can support 0.5 MB, 1MB, 1.5 MB, 2 MB,
3 MB, 3.5 MB and 4 MB of system memory.
Auto Configuration
: Enabled
CPU-PCI Burst Mem.WR : Disabled
L2 Cache Update Mode: WB
ISA Bus Clock Frequence: 7.159 MHz
L2 (WB) Tag Bit Length
: 7bits
System BIOS Cacheable : Enabled
SRAM Back to Back
: Enabled
Video BIOS Cacheable
: Enabled
SRAM Leadoff Timing
: 3 Ck
Memory Hole at 15M-16M : Disabled
DRAM Leadoff Timing
: 6 Ck
VGA Shared Memory Size: 1 MB
MDLE Delay Timing (ns)
: 4
VGA Mem Clock (MHz)
: 55
RAS Active When Refresh : 5 Ck
Linear Mode SRAM Support: Disabled
CAS Delay in Posted-WR : 1 Ck
FP DRAM CAS Pr. Timing : 1 Ck
FP DRAM RAS Pr. Timing : 3 Ck
EDO CAS Pulse Width
: R1 W2 Ck
EDO CAS Precharge Time : 1 Ck
EDO MDLE Timing
: 1 Ck
EDO BRDY# Timing
: 1 Ck
Esc : Quit
↑↓→←
: Select Item
EDO RAS Prech. Timing
: 3 Ck
F1 : Help
PU/PD/+/- : Modify
EDO RAMW# Pwr Saving : Disabled
F5 : Old Values <Shift>F2 : Color
ISA Bus Clock Frequency : PCICLK/4
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
Auto Configuration
: Enabled
L2 (WB) Tag Bit Length
: 8 bits
SRAM Back to Back
: Enabled
NA # Enable
: Enabled
Starting Point of Paging
: 1T
Refresh Cycle Time (US) : 15.6
RAS Pulse Width Refresh : 4T
RAS Precharge Time
: 2T
RAS to CAS Delay
: 2T
CAS # Pulse Width (FP)
: 2T
CAS # Pulse Width (EDO) : 1T
RAMW# Assertion Timing : 3T
CAS Precharge Time (FP) : 1T/2T
CAS Precharge Time (EDO): 1T/2T
Enhanced Memory Write : Disabled
Read Prefetch Memory RD: Enabled
CPU to PCI Post Write
: 4T
