Aeroflex IFR 4000 Maintenance Manual Download

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MAINTENANCE MANUAL
IFR 4000

2-2-1

Page 10

Aug 1/04

(3) External Memory (NVRAM)

There is 256k x32 of NVRAM on the CPU board. It is accessible as bytes, words and
long words (32 bit). The NVRAM is battery backed up by a battery located on the Multi-
Function board. The power and chip select for the NVRAM is controlled by Uxx. This
device monitors the +3.3 V supply voltage and will switch over to battery power and
disable the SRAM chip enable when the supply voltage drops to 2.55 to 2.70 V. Uxx
also provides a battery status output. This signal will go low when the battery voltage
is below 2.5 V. It is checked at power up. This input is read via the status register in
the CPLD.

(4) Reset

Circuit

The Processor PCB Assy contains a voltage supervisory reset circuit. The voltage
supervisory device (U5) provides a reset pulse at power-up and during “brown-out”
conditions. If the +3.3 V drops below 2.55 to 2.70 V, the reset goes low until the
voltage returns to normal. A reset is generated while the reset input is held low.

(5) CPLD

The CPLD controls chip select generation and buffer control for devices on the
Processor PCB Assy and Multi-Function PCB Assy. The CPLD also contains a status
register, F/W version register, clock di vider and a FPGA programming port for the
FPGA on the Multi-Function PCB Assy.

The version register is an 8-bit device that contains the version for the CPLD F/W.
The status register is an 8-bit device that provides the H/W configuration, user
definable jumpers and the NVRAM battery status.

The FPGA on the Multi-Function PCB Assy supports Slave Serial, Master Serial, Slave
Parallel and Boundary Scan mode. In Master Serial, a local (local to the Multi-
Function PCB Assy) serial PROM provides the configuration data. In Slave Parallel
mode, the Processor PCB Assy provides the configuration data. Configuration
resistors on the Multi-Function PCB Assy provide for selecting one of the two
programming methods. If the Multi-Function PCB Assy is strapped for Master Serial
mode, the Processor PCB Assy is not responsible for the FPGA configuration, but can
monitor the status. If the Multi-Function PCB Assy is strapped for Slave Parallel
Mode, the Processor PCB Assy loads the configuration data. There is a FPGA Control
Register, Status Register and Configuration Data port for configuring the FPGA. The
FPGA Configuration Data port accepts data and provides configuration data to the
FPGA.

(6) Serial

Ports

The Processor PCB Assy has two RS-232 ports. Both ports provide RX, TX, RTS and
CTS capability. COMM Port 1 is available as the system port and can be accessed via
the RS-232 Connector. COMM Port 2 is accessed via the TEST Connector. Both
COMM Port signals are at a 3.3 V level.

(7) Bus

Interface

The Bus Interface communicates with the Multi-Function PCB Assy and consists of
address lines A0-A23, data lines D0-D31, R/W, /Reset, CPU Clock, DMA, Timer,
Interrupt, I

C bus, and chip selects. The address, data, reset, clock and chip selects

are buffered. The data bus buffer enable and direction is controlled via the CPLD.