DR500 Operation and Technical Manual
Technical Details
Version 1.6
Aerotech, Inc.
3-3
3.1.1. Pin
Descriptions
The following is a brief description for each pin of the OP500 connector that connects J1
of the DR500 to the U500/U600 CPU board.
For hardware specific information on a signal, refer to your controller’s hardware
manual.
Pin 1 - Interlock Send
The DR500 input is a logic signal driven by the UNIDEX
500/600 to sense the presence of the DR500 Drive
Chassis. UNIDEX 500/U600 drives this line and senses
the signal returned through the drive chassis (on pin 100
interlock receive) to assure the system is properly
connected.
Pin 2 - Amplifier Sync /
Common
The Sync. signal is a logic level square wave output at 20
kilo hertz that drives the PWM current regulators, on the
drive modules, to synchronize the switching of the power
output circuits. This is currently not used by any drive
modules. This pin may also be configured as common.
Pins 3 & 4 - Encoder Power
These +5 volt Encoder Power inputs are not normally
used by the DR500. These connections are used to
provide op5 volt power from the U500/U600
board.
Pins 51, 77, 78, 87
These pins are common to the power supply.
The following pins repeat for all 4 axes. For each set of encoder signals refer to
Figure 3-2 (Motor Phasing) and Figure 3-3 (Linear Motor (Forcer) CW Direction). On
the U500/U600 board, each of the outputs are applied to a differential receiver (26LS32
typical) with a 180 ohm termination resistor across each pair of inputs. In addition, each
of the sine and cosine signal pairs are also connected to an exclusive OR circuit for the
purpose of detecting the loss of encoder signals (this excludes the marker signal pairs).
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